Table of Contents
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 6
Chapter 2. Functional Description ........................................................................................................ 7
Key Concepts........................................................................................................................................................ 7
Block Diagram....................................................................................................................................................... 7
Coefficients ........................................................................................................................................................... 8
Interpolation and Decimation ....................................................................................................................... 8
Coefficient Generation ............................................................................................................................... 10
Dynamic Zoom and Pan...................................................................................................................................... 12
Primary I/O .......................................................................................................................................................... 13
Interface Descriptions ......................................................................................................................................... 13
Video Input/Output ..................................................................................................................................... 13
Coefficient Update...................................................................................................................................... 13
Chapter 3. Parameter Settings ............................................................................................................ 14
Architecture Tab.................................................................................................................................................. 14
Filter Specifications .................................................................................................................................... 15
Interpolation/Decimation Factors ............................................................................................................... 16
Active Region ............................................................................................................................................. 16
Edge Mode................................................................................................................................................. 16
Coefficients Specifications ......................................................................................................................... 16
Throughput................................................................................................................................................. 16
I/O Specification Tab........................................................................................................................................... 17
Input data ................................................................................................................................................... 17
Coefficients ................................................................................................................................................ 17
Vertical Filter Output .................................................................................................................................. 17
Output ........................................................................................................................................................ 17
Precision Control........................................................................................................................................ 18
Implementation Tab ............................................................................................................................................ 18
Memory Type ............................................................................................................................................. 18
Chapter 4. IP Core Generation............................................................................................................. 19
Licensing the IP Core.......................................................................................................................................... 19
Getting Started .................................................................................................................................................... 19
IPexpress-Created Files and Top Level Directory Structure............................................................................... 21
Instantiating the Core .......................................................................................................................................... 23
Running Functional Simulation ........................................................................................................................... 23
Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 23
Hardware Evaluation........................................................................................................................................... 24
Enabling Hardware Evaluation in Diamond................................................................................................ 24
Enabling Hardware Evaluation in ispLEVER.............................................................................................. 24
Updating/Regenerating the IP Core .................................................................................................................... 24
Regenerating an IP Core in Diamond ........................................................................................................ 24
Regenerating an IP Core in ispLEVER ...................................................................................................... 25
Chapter 5. Support Resources ............................................................................................................ 26
Lattice Technical Support.................................................................................................................................... 26
Online Forums............................................................................................................................................ 26
Telephone Support Hotline ........................................................................................................................ 26
E-mail Support ........................................................................................................................................... 26
Local Support ............................................................................................................................................. 26
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG89_1.0, January 2011
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2D FIR Filter IP Core User’s Guide
Lattice Semiconductor
Table of Contents
Internet ....................................................................................................................................................... 26
References.......................................................................................................................................................... 26
LatticeECP2/M ........................................................................................................................................... 26
LatticeECP3 ............................................................................................................................................... 26
LatticeXP2.................................................................................................................................................. 26
Revision History .................................................................................................................................................. 26
Appendix A. Resource Utilization ....................................................................................................... 27
LatticeECP2 Devices .......................................................................................................................................... 27
Ordering Part Number................................................................................................................................ 27
LatticeECP2M Devices ....................................................................................................................................... 28
Ordering Part Number................................................................................................................................ 28
LatticeECP3 Devices .......................................................................................................................................... 28
Ordering Part Number................................................................................................................................ 28
LatticeXP2 Devices ............................................................................................................................................. 29
Ordering Part Number................................................................................................................................ 29
IPUG89_1.0, January 2011
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2D FIR Filter IP Core User’s Guide
Chapter 1:
Introduction
The 2D FIR Filter IP core performs real-time 2D convolution of windowed portions of incoming video frames with
coefficient matrices held in internal memory. Its flexible architecture supports a wide variety of filtering operations
on LatticeECP2™, LatticeECP2M™, LatticeECP3™ and LatticeXP2™ devices. The highly parameterized design
takes advantage of the embedded DSP blocks available in Lattice FPGAs. A simple I/O handshake makes the core
suitable for either streaming or bursty input video data. Coefficients may be set at compile time, or updated in sys-
tem via a simple memory interface.
Quick Facts
Table 1-1
through
Table 1-4
give quick facts about the 2D FIR Filter IP core for LattceECP2, LatticeECP2M,
LatticeECP3, and LatticeXP2 devices.
Table 1-1. 2D FIR Filter Quick Facts for LatticeECP2
Core Requirements
FPGA Family Support
Minimal Device Needed
Target device
Data Path Width
Resource Utilization
LUTs
sysMEM EBRs
sysDSP Blocks
Registers
Lattice Implementation
Design Tool Support
Synthesis
Simulation
3
920
2000
5x5 single-rate,
704x480,
CIRCULAR,
non-separable
2D FIR IP configurations
5x5 single-rate,
704x480, None,
separable
LatticeECP2
LFE2-6E-5T144C
LFE2-50E-6F484C
8
580
2
3
460
Lattice Diamond™ 1.1 or ispLEVER
®
8.1SP1
Synopsys
®
Synplify™ Pro for D-2010.03L-SP1
Aldec
®
Active-HDL
®
8.2 Lattice Edition
Mentor Graphics
®
ModelSim
®
SE 6.3F
2
410
680
5x5 single-rate,
704x480, XANDY,
separable
IPUG89_1.0, January 2011
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2D FIR Filter IP Core User’s Guide
Microcontroller MCU
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