ADL5801-EVALZ datasheet, PDF - EEWORLD Datasheet

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ADL5801-EVALZ: DescriptionRF Development Tools ADL5801 Eval Board; CategoryDevelopment board/suite/development tools; File Size717KB，41 Pages; ManufacturerADI; Websitehttps://www.analog.com; Environmental Compliance

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RF Development Tools ADL5801 Eval Board

ADL5801-EVALZ Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	ADI
Product Category	RF Development Tools
RoHS	Details
Product	Evaluation Boards
Type	RF Mixers
Tool Is For Evaluation Of	ADL5801
Frequency	10 MHz to 6 GHz
Operating Supply Voltage	4.75 V to 5.25 V
Packaging	Bulk
Interface Type	SMA Connector
Factory Pack Quantity	1
Unit Weight	8.818490 oz

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Data Sheet

FEATURES

Broadband upconverter/downconverter

Power conversion gain of 1.8 dB

Broadband RF, LO, and IF ports

SSB noise figure (NF) of 9.75 dB

Input IP3: 28.5 dBm

Input P1dB: 13.3 dBm

Typical LO drive: 0 dBm

Single-supply operation: 5 V at 130 mA

Adjustable bias for low power operation

Exposed paddle, 4 mm × 4 mm, 24-lead LFCSP package

High IP3,

10 MHz to 6 GHz, Active Mixer

ADL5801

FUNCTIONAL BLOCK DIAGRAM

VPLO GND NC IFON IFOP GND

GND

ADL5801

VPRF

GND

RFIP

RFIN

GND

VPDT

LOIP

V2I

LOIN

GND

APPLICATIONS

Cellular base station receivers

Radio link downconverters

Broadband block conversion

Instrumentation

BIAS

DET

08079-001

VPLO GND ENBL VSET DETO GND

Figure 1.

GENERAL DESCRIPTION

The

ADL5801

uses a high linearity, doubly balanced, active

mixer core with integrated LO buffer amplifier to provide high

dynamic range frequency conversion from 10 MHz to 6 GHz.

The mixer benefits from a proprietary linearization architecture

that provides enhanced input IP3 performance when subject to

high input levels. A bias adjust feature allows the input linearity,

SSB noise figure, and dc current to be optimized using a single

control pin. An optional input power detector is provided for

adaptive bias control. The high input linearity allows the device

to be used in demanding cellular applications where in-band

blocking signals may otherwise result in degradation in dynamic

performance. The adaptive bias feature allows the part to provide

high input IP3 performance when presented with large blocking

signals. When blockers are removed, the

ADL5801

can auto-

matically bias down to provide low noise figure and low power

consumption.

The balanced active mixer arrangement provides superb LO-to-

RF and LO-to-IF leakage, typically better than −40 dBm. The IF

outputs are designed to provide a typical voltage conversion

gain of 7.8 dB when loaded into a 200 Ω load. The broad

frequency range of the open-collector IF outputs allows the

ADL5801

to be applied as an upconverter for various transmit

applications.

The

ADL5801

is fabricated using a SiGe high performance IC

process. The device is available in a compact 4 mm × 4 mm,

24-lead LFCSP package and operates over a −40°C to +85°C

temperature range. An evaluation board is also available.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

Document Feedback

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

ADL5801

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Downconverter Mode with a Broadband Balun ...................... 8

Downconverter Mode with a Mini-Circuits® TC1-1-43M+

Input Balun .................................................................................. 12

Downconverter Mode with a Johanson 3.5 GHz

Input Balun .................................................................................. 14

Downconverter Mode with a Johanson 5.7 GHz

Input Balun .................................................................................. 16

Upconverter Mode with a 900 MHz Output Match .............. 18

Upconverter Mode with a 2.1 GHz Output Match ................ 20

Spur Performance ....................................................................... 23

Data Sheet

Circuit Description......................................................................... 27

LO Amplifier and Splitter.......................................................... 27

RF Voltage-to-Current (V-to-I) Converter ............................. 27

Mixer Core .................................................................................. 27

Mixer Output Load .................................................................... 27

RF Detector ................................................................................. 28

Bias Circuit .................................................................................. 28

Applications Information .............................................................. 31

Basic Connections ...................................................................... 31

RF and LO Ports ......................................................................... 31

IF Port .......................................................................................... 32

Downconverting to Low Frequencies ...................................... 33

Broadband Operation ................................................................ 34

Single-Ended Drive of RF and LO Inputs ............................... 36

Evaluation Board ............................................................................ 38

Outline Dimensions ....................................................................... 40

Ordering Guide .......................................................................... 40

REVISION HISTORY

4/14—Rev. D to Rev. E

Changes to Figure 1 .......................................................................... 1

Changes to Table 1 ............................................................................ 4

Changes to Figure 87 and Deleted Table 4; Renumbered

Sequentially ..................................................................................... 27

Changes to RF Detector Section and Bias Circuit Section;

Added Table 4 and Table 5; Renumbered Sequentially, and

Added Figure 92, Figure 93, Figure 94, and Figure 95;

Renumbered Sequentially.............................................................. 29

3/14—Rev. C to Rev. D

Changes to Pin 9, Table 3 ................................................................. 7

8/13—Rev. B to Rev. C

Changes to Table 8 .......................................................................... 38

7/13—Rev. A to Rev. B

Added Disable Voltage and Enable Voltage; Table 1 .................... 3

Changes to Table 5 and Figure 96 ................................................. 31

Added Downconverting to Low Frequencies Section and

Figure 97; Renumbered Sequentially ........................................... 32

Added Broadband Operation Section and Figure 98 to

Figure 101 ........................................................................................ 33

Added Single-Ended Drive of RF and LO Inputs Section and

Figure 102 to Figure 105 ................................................................ 35

Updated Outline Dimensions ....................................................... 39

7/11—Rev. 0 to Rev. A

Changes to Specifications Section ...................................................3

Changes to Typical Performance Characteristics Section ...........8

Changes to Spur Performance Section ........................................ 23

Changes to RF Voltage-to-Current (V-to-I) Converter

Section.............................................................................................. 27

Changes to RF Detector Section................................................... 28

Changes to RF and LO Ports Section........................................... 30

2/10—Revision 0: Initial Version

Rev. E | Page 2 of 40

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