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MUN53xxDW1T1

Description
PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363
Categorysemiconductor    Discrete semiconductor   
File Size246KB,16 Pages
ManufacturerMotorola ( NXP )
Websitehttps://www.nxp.com
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MUN53xxDW1T1 Overview

PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363

MUN53xxDW1T1 Parametric

Parameter NameAttribute value
stateCONSULT MFR
Transistor typeUniversal small signal
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MUN5311DW1T1/D
Dual Bias Resistor Transistors
NPN and PNP Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with a
monolithic bias network consisting of two resistors; a series base resistor and a
base–emitter resistor. These digital transistors are designed to replace a single
device and its external resistor bias network. The BRT eliminates these
individual components by integrating them into a single device. In the
MUN5311DW1T1 series, two complementary BRT devices are housed in the
SOT–363 package which is ideal for low power surface mount applications
where board space is at a premium.
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
Available in 8 mm, 7 inch/3000 Unit Tape and Reel.
MUN5311DW1T1
SERIES
Motorola Preferred Devices
6
5
4
1
2
3
CASE 419B–01, STYLE 1
SOT–363
(3)
R1
Q1
(2)
R2
(1)
Q2
R2
(4)
(5)
R1
(6)
MAXIMUM RATINGS
(TA = 25°C unless otherwise noted, common for Q1 and Q2, – minus sign for Q2 (PNP) omitted)
Rating
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
Symbol
VCBO
VCEO
IC
R
θJA
TJ, Tstg
PD
Marking
11
12
13
14
15
16
30
31
32
33
34
35
R1 (K)
10
22
47
10
10
4.7
1.0
2.2
4.7
4.7
22
2.2
Value
50
50
100
Unit
Vdc
Vdc
mAdc
°C/W
°C
mW
THERMAL CHARACTERISTICS
Thermal Resistance — Junction-to-Ambient (surface mounted)
Operating and Storage Temperature Range
Total Package Dissipation @ TA = 25°C(1)
833
– 65 to +150
*150
DEVICE MARKING AND RESISTOR VALUES: MUN5311DW1T1 SERIES
Device
MUN5311DW1T1
MUN5312DW1T1
MUN5313DW1T1
MUN5314DW1T1
MUN5315DW1T1(2)
MUN5316DW1T1(2)
MUN5330DW1T1(2)
MUN5331DW1T1(2)
MUN5332DW1T1(2)
MUN5333DW1T1(2)
MUN5334DW1T1(2)
MUN5335DW1T1(2)
R2 (K)
10
22
47
47
1.0
2.2
4.7
47
47
47
1. Device mounted on a FR-4 glass epoxy printed circuit board using the minimum recommended footprint.
2. New resistor combinations. Updated curves to follow in subsequent data sheets.
Thermal Clad is a trademark of the Bergquist Company
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 3
Motorola Small–Signal Transistors, FETs and Diodes Device Data
©
Motorola, Inc. 1997
1

MUN53xxDW1T1 Related Products

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Description PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363 PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363 PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363 PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363 PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363 PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363 PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363 PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363 PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363 PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363
Maker - - Motorola ( NXP ) Motorola ( NXP ) Motorola ( NXP ) Motorola ( NXP ) Motorola ( NXP ) Motorola ( NXP ) Motorola ( NXP ) Motorola ( NXP )
package instruction - - SMALL OUTLINE, R-PDSO-G6 SMALL OUTLINE, R-PDSO-G6 SMALL OUTLINE, R-PDSO-G6 SMALL OUTLINE, R-PDSO-G6 SMALL OUTLINE, R-PDSO-G6 SMALL OUTLINE, R-PDSO-G6 SMALL OUTLINE, R-PDSO-G6 SMALL OUTLINE, R-PDSO-G6
Reach Compliance Code - - unknow unknow unknow unknown unknow unknow unknow unknow
Other features - - BUILT-IN BIAS RESISTOR RATIO IS 10 BUILT-IN BIAS RESISTOR RATIO IS 1 BUILT-IN BIAS RESISTOR RATIO IS 1 - - BUILT-IN BIAS RESISTOR RATIO IS 1 BUILT-IN BIAS RESISTOR RATIO IS 1 BUILT-IN BIAS RESISTOR RATIO IS 1
Maximum collector current (IC) - - 0.1 A 0.1 A 0.1 A 0.1 A 0.1 A 0.1 A 0.1 A 0.1 A
Collector-emitter maximum voltage - - 50 V 50 V 50 V 50 V 50 V 50 V 50 V 50 V
Configuration - - SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR
Minimum DC current gain (hFE) - - 80 15 8 160 160 80 60 35
JESD-30 code - - R-PDSO-G6 R-PDSO-G6 R-PDSO-G6 R-PDSO-G6 R-PDSO-G6 R-PDSO-G6 R-PDSO-G6 R-PDSO-G6
JESD-609 code - - e0 e0 e0 e0 e0 e0 e0 e0
Number of components - - 2 2 2 2 2 2 2 2
Number of terminals - - 6 6 6 6 6 6 6 6
Maximum operating temperature - - 150 °C 150 °C 150 °C 150 °C 150 °C 150 °C 150 °C 150 °C
Package body material - - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
Package shape - - RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form - - SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
Polarity/channel type - - NPN AND PNP NPN AND PNP NPN AND PNP NPN AND PNP NPN AND PNP NPN AND PNP NPN AND PNP NPN AND PNP
Maximum power consumption environment - - 0.15 W 0.15 W 0.15 W 0.15 W 0.15 W 0.15 W 0.15 W 0.15 W
Maximum power dissipation(Abs) - - 0.15 W 0.15 W 0.15 W 0.15 W 0.15 W 0.15 W 0.15 W -
Certification status - - Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
surface mount - - YES YES YES YES YES YES YES YES
Terminal surface - - Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form - - GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal location - - DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL
Transistor component materials - - SILICON SILICON SILICON SILICON SILICON SILICON SILICON SILICON

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