EEWORLDEEWORLDEEWORLD

Part Number

Search

8N3Q001LG-0151CDI

Description
Programmable Oscillators PROGRAMMABLE 5X7 OSCILLATOR
CategoryPassive components   
File Size170KB,21 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

8N3Q001LG-0151CDI Online Shopping

Suppliers Part Number Price MOQ In stock  
8N3Q001LG-0151CDI - - View Buy Now

8N3Q001LG-0151CDI Overview

Programmable Oscillators PROGRAMMABLE 5X7 OSCILLATOR

8N3Q001LG-0151CDI Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerIDT (Integrated Device Technology)
Product CategoryProgrammable Oscillators
ProductXO
Package / Case7 mm x 5 mm
Length7 mm
Width5 mm
Height1.55 mm
PackagingTube
Factory Pack Quantity364
Unit Weight0.006562 oz
Quad-Frequency Programmable XO IDT8N3Q001 REV G
DATA SHEET
General Description
The IDT8N3Q001 is a Quad-Frequency Programmable Clock
Oscillator with very flexible frequency programming capabilities. The
device uses IDT’s fourth generation FemtoClock® NG technology for
an optimum of high clock frequency and low phase noise
performance. The device accepts 2.5V or 3.3V supply and is
packaged in a small, lead-free (RoHS 6) 10-lead Ceramic 5mm x
7mm x 1.55mm package.
Besides the four default power-up frequencies set by the FSEL0 and
FSEL1 pins, the IDT8N3Q001 can be programmed via the I
2
C
interface to output clock frequencies between 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz to a very high degree of
precision with a frequency step size of 435.9Hz ÷
N
(N is the PLL
output divider). Since the FSEL0 and FSEL1 pins are mapped to 4
independent PLL M and N divider registers (P, MINT, MFRAC and N),
reprogramming those registers to other frequencies under control of
FSEL0 and FSEL1 is supported. The extended temperature range
supports wireless infrastructure, telecommunication and networking
end equipment requirements.
Features
Fourth generation FemtoClock® NG technology
Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
Four power-up default frequencies (see part number order
codes), re-programmable by I
2
C
I
2
C programming interface for the output clock frequency and
internal PLL control registers
Frequency programming resolution is 435.9Hz ÷N
One 2.5V, 3.3V LVPECL clock output
Two control inputs for the power-up default frequency
LVCMOS/LVTTL compatible control inputs
RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.244ps
(typical), integer PLL feedback configuration
RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.265ps
(typical), integer PLL feedback configuration
Full 2.5V or 3.3V supply modes
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
Block Diagram
OSC
f
XTAL
÷MINT,
MFRAC
2
25
FSEL1
FSEL0
SCLK
SDATA
OE
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pin Assignment
÷P
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷N
Q
nQ
DNU 1
OE 2
V
EE
3
FSEL0 4
FSEL1 5
10 SCLK
9 SDATA
8 V
CC
7 nQ
6 Q
7
Configuration Register (ROM)
(Frequency, APR, Polarity)
I
2
C Control
IDT8N3Q001
10-lead Ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
1
©2012 Integrated Device Technology, Inc.
Many thanks
When making a radio-controlled clock based on a single-chip microcomputer, how can we use the radio signal in the air to realize the automatic calibration function? ? ? ?...
1564222166 51mcu
GSM Mobile Phone RF Test Guide
[i=s]This post was last edited by jameswangsynnex on 2015-3-3 19:58[/i] GSM Mobile Phone RF Test Guide...
emily Mobile and portable
2006 Sichuan Province Undergraduate Electronic Design Competition Questions - Simple Digital Frequency Meter (Neijiang Normal University)
[i=s]This post was last edited by paulhyde on 2014-9-15 09:46[/i] [b]Electronic Design Competition Test Questions Simple Digital Frequency Meter I. Electronic Design Competition Design Task: [/b] Desi...
呱呱 Electronics Design Contest
[Altera SOC in-depth experience tour] FPGA and me
[i=s] This post was last edited by bsdlinux on 2015-2-1 05:54 [/i] [align=left][color=#000][font=Simsun][size=3] When I was in college, I first came into contact with FPGA. I couldn't sleep for many n...
bsdlinux FPGA/CPLD
EEWORLD University Hall----SensorTile Competition - Weather Monitoring
SensorTile Competition - Weather Monitoring : https://training.eeworld.com.cn/course/4057...
supermiao123 Test/Measurement
A New Inrush Current Limiter
Abstract: The defects of traditional surge current limiting methods are pointed out, such as high power consumption, secondary surge and non-function. A new method of surge current limiting is propose...
zbz0529 Power technology

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1366  825  1908  1639  2049  28  17  39  33  42 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号