PI6C4911510
2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL
Fanout Buffer with 2 to 1 Differential Clock Input Mux
Features
ÎÎ
MAX
< 1.5GHz
F
ÎÎ
pairs of differential LVPECL outputs
10
ÎÎ
Low additive jitter, < 0.03ps (typ)
ÎÎ
Selectable differential input pairs with single ended
Description
The PI6C4911510 is a high-performance low-skew 1-to-10 LVPECL
fanout buffer. The PI6C4911510 features two selectable dif-
ferential clock inputs and translates to ten LVPECL outputs.
The CLK inputs accept LVPECL, LVDS, CML and SSTL signals.
PI6C4911510 is ideal for clock distribution applications such as
providing fanout for low noise SaRonix-eCera oscillators.
option
input
ÎÎ
Input CLK accepts: LVPECL, LVDS, CML, SSTL input level
ÎÎ
Output skew: 40ps (typ)
ÎÎ
Operating Temperature: -40
o
C to 85
o
C
ÎÎ
Core Power supply: 2.5V ±5% & 3.3V ±10%, Output Power
supply: 2.5V ±5% & 3.3V ±10%
ÎÎ
Packaging (Pb-free & Green):
ÎÎ
32-pin
QFN and TQFP available
Block Diagram
Pin Configuration
V
DDO
/Q2
Q2
/Q1
Q1
/Q0
Q0
v
DDO
24 23 22 21 20 19 18 17
16
25
15
26
14
27
13
28
29
30
31
32
12
11
10
1 2 3
CLK_SEL
CLK0
Q3
/Q3
Q4
/Q4
Q5
/Q5
Q6
/Q6
4
/CLK0
5
6
CLK1
7 8
/CLK1
9
v
DDO
Q7
/Q7
Q8
/Q8
Q9
/Q9
v
DDO
15-0077
1
V
BB
(NC)
V
DD
PI6C4911510
V
EE
Rev H
6/25/2015
2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to
LVPECL Fanout Buffer w/ 2 to 1 Differential Clock Input Mux
Pin Description
(1)
Pin #
1
2
3
4
5
6
7
8
9, 16, 25, 32
11, 10
13,12
15,14
18,17
20,19
22,21
24, 23
27,26
29,28
31,30
PI6C4911510
Name
V
DD
CLK_SEL
CLK0
/CLK0
V
BB
(NC)
CLK1
/CLK1
V
EE
V
DDO
Q9,
/
Q9
Q8,
/
Q8
Q7,
/
Q7
Q6,
/
Q6
Q5,
/
Q5
Q4,
/
Q4
Q3,
/
Q3
Q2,
/
Q2
Q1,
/
Q1
Q0,
/
Q0
Type
Power
Input
Input
Input
Power
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Description
Core Power Supply
Clock select input. When high, selects CLK1 input. When low, selects CLK0 input.
LVCMOS/LVTTL level with 50kΩ pull down.
Differential clock input with pull-down
Inverting differential clock input. Defaults to VDD/2 if left floating.
Internal Common Mode Voltage, can be left as not connected if unused.
Differential clock input with pull-down
Inverting differential clock input. Defaults to VDD/2 if left floating.
Connect to negative power supply
Output Power pin
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Note:
1. I = Input, O = Output, P = Power supply connection.
Control Input Function Table
CLK_SEL
0
1
Outputs
CLK0
CLK1
15-0077
2
PI6C4911510
Rev H
6/25/2015
2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to
LVPECL Fanout Buffer w/ 2 to 1 Differential Clock Input Mux
Absolute Maximum Ratings
(1)
Symbol
V
DD
V
IN
IOUT
T
STG
V
BB
T
j
PI6C4911510
Parameter
Supply voltage
Input voltage
Surge Current
Storage temperature
Sink/source Current, I
BB
Junction Temperature
Conditions
Referenced to GND
Referenced to GND
Min
-0.5
-55
-0.5
Typ
Max
4.6
V
DD
+0.5V
100
150
+0.5
125
Units
V
V
mA
o
C
mA
o
C
Note:
1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These ratings are stress specifica-
tions only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Operating Conditions
Symbol
V
DD
V
DDO
T
A
I
DD
I
DDO
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Ambient Temperature
Core Power Supply Current
Output Power Supply Current
Conditions
Min
2.375
2.375
-40
Typ
Max
3.6
3.6
85
Units
V
V
o
C
70
All LVPECL outputs
unloaded
110
95
200
mA
LVCMOS/LVTTL DC Characteristics
(TA = -40
o
C to +85
o
C, VDD = 3.3V ±10%, VDDO = 2.5V ±5% to 3.3V
±10%)
Symbol
V
IH
V
IL
I
IH
I
IL
R
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_SEL
CLK_SEL
CLK_SEL
CLK_SEL
Conditions
Min
1.7
-0.3
Typ
Max
V
DD
+0.3
150
Units
V
μA
μA
kΩ
V
IN
= V
DD
= 3.6V
V
IN
= 0V, V
DD
= 3.6V
-150
50
Input Pullup/Pulldown Resistance
15-0077
3
PI6C4911510
Rev H
6/25/2015
2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to
LVPECL Fanout Buffer w/ 2 to 1 Differential Clock Input Mux
PI6C4911510
LVPECL DC Characteristics
(T
A
= -40
o
C to +85
o
C, V
DD
= 3.3V ±10%, V
DDO
= 2.5V ±5% to 3.3V ±10%)
Symbol
I
IH
I
IL
V
CMR
V
OH
V
OL
R
Notes:
1. For single-ended applications, the maximum input voltage for CLK and /CLK is V
DD
+0.3V
2. Outputs terminated with 50Ω to V
DD
-2.0V
Parameter
Input High
Current
Input Low Cur-
rent
CLK0, CLK1
/CLK0, /CLK1
CLK0, CLK1
/CLK0, /CLK1
Conditions
V
IN
= V
DD
= 3.6V
V
IN
= V
DD
= 3.6V
V
DD
= 3.6V, V
IN
= 0V
V
DD
= 3.6V, V
IN
= 0V
Min
Typ
Max
150
150
Units
µA
µA
µA
µA
-150
-150
V
EE
+0.5
V
DD
V
DDO
-1.4
V
DDO
-2.0
50
V
DDO
-0.9
V
DDO
-1.7
Common Mode Input Voltage
(1)
Output High Voltage
(2)
Output Low Voltage
(2)
Input Pullup/Pulldown Resistance
V
DDO
= 2.5V or 3.3V
V
DDO
= 2.5V or 3.3V
V
V
V
kΩ
V
DDO
-
1.5
V
DDO
-
2.2
AC Characteristics
(TA = -40
o
C to +85
o
C, VDD = 3.3V ±10%, VDDO = 2.5V ±5% to 3.3V ±10%)
Symbol
f
max
t
pd
Tsk
t
r
/t
f
t
odc
V
PP
Parameter
Output Frequency
Propagation Delay
(1)
Output-to-output Skew
(2)
Output Rise/Fall time
Output duty cycle
Output Swing
Conditions
Min
Typ
1200
40
Max
1500
Units
MHz
ps
ps
ps
20% - 80%
f ≤ 650 MHz
LVPECL outputs
156.25MHz (12KHz-
20MHz integration range)
48
0.6
150
52
1.0
%
V
t
j
Buffer additive jitter RMS
Input condition per Phase
Noise and Additive Jitter
Plot below
0.03
0.05
ps
Notes:
1. Measured from the differential input to the differential output crossing point
2. Defined as skew between outputs at the same supply voltage and with equal loads. Measured at the output differential crossing point
15-0077
4
PI6C4911510
Rev H
6/25/2015
2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to
LVPECL Fanout Buffer w/ 2 to 1 Differential Clock Input Mux
Phase Noise and Additive Jitter
Output phase noise (Dark Blue) vs Input Phase noise (light blue)
Additive jitter is calculated at ~27fs RMS (12kHz to 20MHz). Additive jitter = √(Output jitter
2
- Input jitter
2
)
PI6C4911510
Configuration Test Load Board Termination for LVPECL Outputs
LVPECL Buffer
V
DDQx
Z o = 50
L = 0 ~ 10 in.
100
Z o = 50
150
150
15-0077
5
PI6C4911510
Rev H
6/25/2015
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