82V2088DRG datasheet, PDF - EEWORLD Datasheet

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82V2088DRG: DescriptionTelecom Interface ICs OCTAL LH LIU; CategoryWireless rf/communication Telecom circuit; File Size720KB，78 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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Telecom Interface ICs OCTAL LH LIU

82V2088DRG Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	PQFP
package instruction	FQFP, QFP208,1.2SQ,20
Contacts	208
Manufacturer packaging code	DRG208
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	S-PQFP-G208
JESD-609 code	e3
length	28 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	208
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Encapsulate equivalent code	QFP208,1.2SQ,20
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	4.07 mm
Maximum slew rate	0.73 mA
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	PCM TRANSCEIVER
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	28 mm

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OCTAL CHANNEL T1/E1/J1 LONG HAUL/

SHORT HAUL LINE INTERFACE UNIT

IDT82V2088

FEATURES:

•

Eight channel T1/E1/J1 long haul/short haul line interfaces

Supports HPS (Hitless Protection Switching) for 1+1 protection

without external relays

Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024

KHz

Programmable T1/E1/J1 switchability allowing one bill of ma-

terial for any line condition

Single 3.3 V power supply with 5 V tolerance on digital interfaces

Meets or exceeds specifications in

ANSI T1.102, T1.403 and T1.408

- ITU I.431, G.703,G.736, G.775 and G.823

- ETSI 300-166, 300-233 and TBR 12/13

- AT&T Pub 62411

Per channel software selectable on:

- Wave-shaping templates for short haul and long haul LBO (Line Build

Out)

- Line terminating impedance (T1:100

,

J1:110

E1:75 120 

- Adjustment of arbitrary pulse shape

- JA (Jitter Attenuator) position (receive path or transmit path)

- Single rail/dual rail system interfaces

B8ZS/HDB3/AMI line encoding/decoding

- Active edge of transmit clock (TCLK) and receive clock (RCLK)

Active level of transmit data (TDATA) and receive data (RDATA)

Receiver or transmitter power down

High impedance setting for line drivers

PRBS (Pseudo Random Bit Sequence) generation and detection

with 2

-1 PRBS polynomials for E1

- QRSS (Quasi Random Sequence Signals) generation and detection

with 2

-1 QRSS polynomials for T1/J1

- 16-bit BPV (Bipolar Pulse Violation)/Excess Zero/PRBS or QRSS

error counter

- Analog loopback, Digital loopback, Remote loopback and Inband

loopback

Per channel cable attenuation indication

Adaptive receive sensitivity

Non-intrusive monitoring per ITU G.772 specification

Short circuit protection for line drivers

LOS (Loss Of Signal) & AIS (Alarm Indication Signal) detection

JTAG interface

Supports serial control interface, Motorola and Intel Non-Multi-

plexed interfaces

Package:

IDT82V2088: 208-pin PQFP and 208-pin PBGA

•

DESCRIPTION:

The IDT82V2088 can be configured as an octal T1, octal E1 or octal J1

Line Interface Unit. In receive path, an Adaptive Equalizer is integrated to

remove the distortion introduced by the cable attenuation. The IDT82V2088

also performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and

detects and reports the LOS conditions. In transmit path, there is an AMI/

B8ZS/HDB3 encoder, Waveform Shaper and LBOs. There is one Jitter

Attenuator for each channel, which can be placed in either the receive path

or the transmit path. The Jitter Attenuator can also be disabled. The

IDT82V2088 supports both Single Rail and Dual Rail system interfaces and

both serial and parallel control interfaces. To facilitate the network mainte-

nance, a PRBS/QRSS generation/detection circuit is integrated in each

channel, and different types of loopbacks can be set on a per channel basis.

Four different kinds of line terminating impedance, 75, 100

110 and

120

are

selectable on a per channel basis. The chip also provides driver

short-circuit protection and supports JTAG boundary scanning.

The IDT82V2088 can be used in SDH/SONET, LAN, WAN, Routers,

Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay

Access Devices, CSU/DSU equipment, etc.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGES

November 2012

DSC-6043/5



OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

TABLE OF CONTENTS

IDT82V2088 PIN CONFIGURATIONS .......................................................................................... 8

PIN DESCRIPTION ..................................................................................................................... 10

FUNCTIONAL DESCRIPTION .................................................................................................... 16

3.1

T1/E1/J1 MODE SELECTION .......................................................................................... 16

3.2

TRANSMIT PATH ............................................................................................................. 16

3.2.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 16

3.2.2 ENCODER .............................................................................................................. 16

3.2.3 PULSE SHAPER .................................................................................................... 16

3.2.3.1 Preset Pulse Templates .......................................................................... 16

3.2.3.2 LBO (Line Build Out) ............................................................................... 17

3.2.3.3 User-Programmable Arbitrary Waveform ................................................ 17

3.2.4 TRANSMIT PATH LINE INTERFACE..................................................................... 21

3.2.5 TRANSMIT PATH POWER DOWN ........................................................................ 21

3.3

RECEIVE PATH ............................................................................................................... 22

3.3.1 RECEIVE INTERNAL TERMINATION.................................................................... 22

3.3.2 LINE MONITOR ...................................................................................................... 23

3.3.3 ADAPTIVE EQUALIZER......................................................................................... 23

3.3.4 RECEIVE SENSITIVITY ......................................................................................... 23

3.3.5 DATA SLICER ........................................................................................................ 23

3.3.6 CDR (Clock & Data Recovery)................................................................................ 23

3.3.7 DECODER .............................................................................................................. 23

3.3.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 23

3.3.9 RECEIVE PATH POWER DOWN........................................................................... 23

3.3.10 G.772 NON-INTRUSIVE MONITORING ................................................................ 24

3.4

JITTER ATTENUATOR .................................................................................................... 25

3.4.1 JITTER ATTENUATION FUNCTION DESCRIPTION ............................................ 25

3.4.2 JITTER ATTENUATOR PERFORMANCE ............................................................. 25

3.5

LOS AND AIS DETECTION ............................................................................................. 26

3.5.1 LOS DETECTION ................................................................................................... 26

3.5.2 AIS DETECTION .................................................................................................... 27

3.6

TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 28

3.6.1 TRANSMIT ALL ONES ........................................................................................... 28

3.6.2 TRANSMIT ALL ZEROS......................................................................................... 28

3.6.3 PRBS/QRSS GENERATION AND DETECTION.................................................... 28

3.7

LOOPBACK ...................................................................................................................... 28

3.7.1 ANALOG LOOPBACK ............................................................................................ 28

3.7.2 DIGITAL LOOPBACK ............................................................................................. 28

3.7.3 REMOTE LOOPBACK............................................................................................ 28

3.7.4 INBAND LOOPBACK.............................................................................................. 30

3.7.4.1 Transmit Activate/Deactivate Loopback Code......................................... 30

3.7.4.2 Receive Activate/Deactivate Loopback Code.......................................... 30

3.7.4.3 Automatic Remote Loopback .................................................................. 30

OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

3.8

3.9

3.10

3.11

3.12

3.13

3.14

3.15

3.16

ERROR DETECTION/COUNTING AND INSERTION ...................................................... 31

3.8.1 DEFINITION OF LINE CODING ERROR ............................................................... 31

3.8.2 ERROR DETECTION AND COUNTING ................................................................ 31

3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 32

LINE DRIVER FAILURE MONITORING ........................................................................... 32

MCLK AND TCLK ............................................................................................................. 33

3.10.1 MASTER CLOCK (MCLK) ...................................................................................... 33

3.10.2 TRANSMIT CLOCK (TCLK).................................................................................... 33

MICROCONTROLLER INTERFACES ............................................................................. 34

3.11.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 34

3.11.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 34

INTERRUPT HANDLING .................................................................................................. 35

GENERAL PURPOSE I/O ................................................................................................ 36

5V TOLERANT I/O PINS .................................................................................................. 36

RESET OPERATION ........................................................................................................ 36

POWER SUPPLY ............................................................................................................. 36

PROGRAMMING INFORMATION .............................................................................................. 37

4.1

4.2

4.2.1 GLOBAL REGISTERS............................................................................................ 39

4.2.2 JITTER ATTENUATION CONTROL REGISTER ................................................... 41

4.2.3 TRANSMIT PATH CONTROL REGISTERS........................................................... 41

4.2.4 RECEIVE PATH CONTROL REGISTERS ............................................................. 43

4.2.5 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 45

4.2.6 INTERRUPT CONTROL REGISTERS ................................................................... 48

4.2.7 LINE STATUS REGISTERS ................................................................................... 51

4.2.8 INTERRUPT STATUS REGISTERS ...................................................................... 54

4.2.9 COUNTER REGISTERS ........................................................................................ 55

4.2.10 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 56

IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 57

5.1

JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 58

5.2

JTAG DATA REGISTER ................................................................................................... 58

5.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 58

5.2.2 BYPASS REGISTER (BR)...................................................................................... 58

5.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 58

5.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 59

TEST SPECIFICATIONS ............................................................................................................ 61

MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 73

7.1

SERIAL INTERFACE TIMING .......................................................................................... 73

7.2

PARALLEL INTERFACE TIMING ..................................................................................... 74

OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

LIST OF TABLES

Table-1

Table-2

Table-3

Table-4

Table-5

Table-6

Table-7

Table-8

Table-9

Table-10

Table-11

Table-12

Table-13

Table-14

Table-15

Table-16

Table-17

Table-18

Table-19

Table-20

Table-21

Table-22

Table-23

Table-24

Table-25

Table-26

Table-27

Table-28

Table-29

Table-30

Table-31

Table-32

Table-33

Table-34

Table-35

Table-36

Table-37

Table-38

Table-39

Table-40

Pin Description ..............................................................................................................

Transmit Waveform Value For E1 75



........................................................................

Transmit Waveform Value For E1 120



......................................................................

Transmit Waveform Value For T1 0~133 ft...................................................................

Transmit Waveform Value For T1 133~266 ft...............................................................

Transmit Waveform Value For T1 266~399 ft...............................................................

Transmit Waveform Value For T1 399~533 ft...............................................................

Transmit Waveform Value For T1 533~655 ft...............................................................

Transmit Waveform Value For J1 0~655 ft ...................................................................

Transmit Waveform Value For DS1 0 dB LBO..............................................................

Transmit Waveform Value For DS1 -7.5 dB LBO .........................................................

Transmit Waveform Value For DS1 -15.0 dB LBO .......................................................

Transmit Waveform Value For DS1 -22.5 dB LBO .......................................................

Impedance Matching for Transmitter ............................................................................

Impedance Matching for Receiver ................................................................................

Criteria of Starting Speed Adjustment...........................................................................

LOS Declare and Clear Criteria for Short Haul Mode ...................................................

LOS Declare and Clear Criteria for Long Haul Mode....................................................

AIS Condition ................................................................................................................

Criteria for Setting/Clearing the PRBS_S Bit ................................................................

EXZ Definition ...............................................................................................................

Interrupt Event...............................................................................................................

Global Register List and Map........................................................................................

Per Channel Register List and Map ..............................................................................

ID: Chip Revision Register ............................................................................................

RST: Reset Register .....................................................................................................

GCF0: Global Configuration Register 0 ........................................................................

GCF1: Global Configuration Register 1 ........................................................................

INTCH: Interrupt Channel Indication Register...............................................................

GPIO: General Purpose IO Pin Definition Register.......................................................

JACF: Jitter Attenuator Configuration Register .............................................................

TCF0: Transmitter Configuration Register 0 .................................................................

TCF1: Transmitter Configuration Register 1 .................................................................

TCF2: Transmitter Configuration Register 2 .................................................................

TCF3: Transmitter Configuration Register 3 .................................................................

TCF4: Transmitter Configuration Register 4 .................................................................

RCF0: Receiver Configuration Register 0.....................................................................

RCF1: Receiver Configuration Register 1.....................................................................

RCF2: Receiver Configuration Register 2.....................................................................

MAINT0: Maintenance Function Control Register 0......................................................

82V2088DRG Related Products

	82V2088DRG	82V2088BB	82V2088BBG
Description	Telecom Interface ICs OCTAL LH LIU	Telecom Interface ICs OCTAL LH LIU	Telecom Interface ICs OCTAL LH LIU
Is it lead-free?	Lead free	Contains lead	Lead free
Is it Rohs certified?	conform to	incompatible	conform to
Parts packaging code	PQFP	BGA	PBGA
package instruction	FQFP, QFP208,1.2SQ,20	BGA, BGA208,16X16,40	BGA, BGA208,16X16,40
Contacts	208	208	208
Reach Compliance Code	compliant	not_compliant	compliant
ECCN code	EAR99	EAR99	EAR99
JESD-30 code	S-PQFP-G208	S-PBGA-B208	S-PBGA-B208
JESD-609 code	e3	e0	e1
length	28 mm	17 mm	17 mm
Humidity sensitivity level	3	3	3
Number of functions	1	1	1
Number of terminals	208	208	208
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	FQFP	BGA	BGA
Encapsulate equivalent code	QFP208,1.2SQ,20	BGA208,16X16,40	BGA208,16X16,40
Package shape	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, FINE PITCH	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	260	225	260
power supply	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.07 mm	1.97 mm	1.97 mm
Maximum slew rate	0.73 mA	0.73 mA	0.73 mA
Nominal supply voltage	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
Telecom integrated circuit types	PCM TRANSCEIVER	PCM TRANSCEIVER	PCM TRANSCEIVER
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn)	Tin/Lead (Sn63Pb37)	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	GULL WING	BALL	BALL
Terminal pitch	0.5 mm	1 mm	1 mm
Terminal location	QUAD	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	20	30
width	28 mm	17 mm	17 mm
Brand Name	Integrated Device Technology	-	Integrated Device Technology
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	-
Manufacturer packaging code	DRG208	-	BBG208

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