EEWORLDEEWORLDEEWORLD

Part Number

Search

8T49N242-998NLGI#

Description
Clock Generators & Support Products FemtoClock NG Frequency Translator
Categorysemiconductor    Analog mixed-signal IC   
File Size1MB,67 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric Compare View All

8T49N242-998NLGI# Overview

Clock Generators & Support Products FemtoClock NG Frequency Translator

8T49N242-998NLGI# Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerIDT (Integrated Device Technology)
Product CategoryClock Generators & Support Products
RoHSDetails
PackagingReel
Factory Pack Quantity5000
FemtoClock
®
NG Universal Frequency
Translator
Description
The 8T49N242 has one fractional-feedback PLL that can be used as
a jitter attenuator and frequency translator. It is equipped with four
integer output dividers, allowing the generation of up to four different
output frequencies, ranging from 8kHz to 1GHz. These frequencies
are completely independent of the input reference frequencies, and
the crystal reference frequency. The device places virtually no
constraints on input to output frequency conversion, supporting all
FEC rates, including the new revision of ITU-T Recommendation
G.709 (2009), most with 0ppm conversion error. The outputs may
select among LVPECL, LVDS, HCSL or LVCMOS output levels.
This makes it ideal to be used in any frequency synthesis application,
including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and
SONET/SDH, including ITU-T G.709 (2009) FEC rates.
The 8T49N242 accepts up to two differential or single-ended input
clocks and a fundamental-mode crystal input. The internal PLL can
lock to either of the input reference clocks or just to the crystal to
behave as a frequency synthesizer. The PLL can use the second
input for redundant backup of the primary input reference, but in this
case, both input clock references must be related in frequency.
The device supports hitless reference switching between input
clocks. The device monitors both input clocks for Loss of Signal
(LOS), and generates an alarm when an input clock failure is
detected. Automatic and manual hitless reference switching options
are supported. LOS behavior can be set to support gapped or
un-gapped clocks.
The 8T49N242 supports holdover. The holdover has an initial
accuracy of ±50ppB from the point where the loss of all applicable
input reference(s) has been detected. It maintains a historical
average operating point for the PLL that may be returned to in
holdover at a limited phase slope.
The PLL has a register-selectable loop bandwidth from 0.2Hz to
6.4kHz.
The device supports Output Enable & Clock Select inputs and Lock,
Holdover & LOS status outputs.
The device is programmable through an I
2
C interface. It also supports
I
2
C master capability to allow the register configuration to be read
from an external EEPROM.
Programming with IDT’s
Timing Commander
software is
recommended for optimal device performance. Factory
pre-programmed devices are also available.
8T49N242
Datasheet
Typical Applications
• OTN or SONET / SDH equipment
• Gigabit and Terabit IP switches / routers including Synchronous
Ethernet
• Video broadcast
Features
• Supports SDH/SONET and Synchronous Ethernet clocks including
all FEC rate conversions
• 0.35ps RMS Typical Jitter (including spurs): 12kHz to 20MHz
• Operating Modes: Synthesizer, Jitter Attenuator
• Operates from a 10MHz to 50MHz fundamental-mode crystal or a
10MHz to 125MHz external oscillator
• Initial holdover accuracy of +50ppb.
• Accepts up to 2 LVPECL, LVDS, LVHSTL or LVCMOS input clocks
• Accepts frequencies ranging from 8kHz to 875MHz
• Auto and manual clock selection with hitless switching
• Clock input monitoring including support for gapped clocks
• Phase-slope limiting and fully hitless switching options to control
output clock phase transients
• Generates four LVPECL / LVDS / HCSL or eight LVCMOS output
clocks
• Output frequencies ranging from 8kHz up to 1.0GHz
(differential)
• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
• Integer divider ranging from ÷4 to ÷786,420 for each output
• Programmable loop bandwidth settings from 0.2Hz to 6.4kHz
• Optional fast-lock function
• Four General Purpose I/O pins with optional support for status &
control:
• Two Output Enable control inputs provide control over the four
clocks
• Manual clock selection control input
• Lock, Holdover and Loss-of-Signal alarm outputs
• Open-drain Interrupt pin
• Register programmable through I
2
C or via external I
2
C EEPROM
• Full 2.5V or 3.3V supply modes, 1.8V support for LVCMOS outputs,
GPIO and control pins
• -40°C to 85°C ambient operating temperature
• Package: 40-VFQFPN, lead-free (RoHS 6)
©2018 Integrated Device Technology, Inc.
1
January 31, 2018

8T49N242-998NLGI# Related Products

8T49N242-998NLGI# 8T49N242-999NLGI# 8T49N242-998NLGI8
Description Clock Generators & Support Products FemtoClock NG Frequency Translator Clock Generators & Support Products FemtoClock NG Frequency Translator Clock Generators & Support Products UFT 4 Integer Output 0.35ps EEProm 25MHz
Product Attribute Attribute Value Attribute Value -
Manufacturer IDT (Integrated Device Technology) IDT (Integrated Device Technology) -
Product Category Clock Generators & Support Products Clock Generators & Support Products -
RoHS Details Details -
Packaging Reel Reel -
Factory Pack Quantity 5000 5000 -
Prize live broadcast: Registration for NXP's RT06F-based facial recognition technology solution is now open!
Award-winning live broadcast: NXP's facial recognition technology solution based on RT06FClick here to registerLive broadcast time: 20 May 2021 (Thursday) 14:00-15:30 Contents: In recent years, techno...
橙色凯 RF/Wirelessly
About the TSU6721 chip
[i=s] This post was last edited by dontium on 2015-1-23 11:23 [/i]As the project owner requires us to use this chip, I looked up some information today, but I don't fully understand it. I hope someone...
dongjie_0000 Analogue and Mixed Signal
Are you still worried about embedded programming? Please read this book "C Embedded Programming Design Patterns"
[size=4]Are you still worried about embedded programming? Please read this book "C Embedded Programming Design Patterns" [/size] [size=4] [/size] [size=4][color=#666666][font=verdana, 宋体]With the rapi...
tiankai001 Download Centre
Linux scan code, conversion between virtual codes
On PC, you can use xmodmap to convert scan codes and virtual codes. But it seems that it can only convert the output of /dev/ttyx device. Now I have a USB keyboard, /dev/input/eventx, and the value re...
lzwml Linux and Android
Can anyone help me write a program for the 6M crystal clock of the AT89C51 microcontroller? C language is preferred, please!
I hope you can help me solve the problem of AT89C51 MCU 6M crystal clock. Can anyone help me write the program? C language is preferred. Please help me! Also, how is the LED connected? Please answer t...
sunpat 51mcu
Ask: Problem with ADC12 module, urgent!!!
A0results[index] = ADC12MEM0; // Move A0 results, IFG is clearedA1results[index] = ADC12MEM1; // Move A1 results, IFG is clearedA2results[index] = ADC12MEM2; // Move A2 results, IFG is clearedA3result...
小李啧 Microcontroller MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 913  2822  1518  1023  2076  19  57  31  21  42 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号