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74LVX20MTR

Description
Logic Gates Dual 4-Input NAND
Categorylogic    logic   
File Size171KB,11 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Environmental Compliance
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74LVX20MTR Overview

Logic Gates Dual 4-Input NAND

74LVX20MTR Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSTMicroelectronics
Parts packaging codeSOIC
package instructionSOP, SOP14,.25
Contacts14
Reach Compliance Codecompliant
seriesLV/LV-A/LVX/H
JESD-30 codeR-PDSO-G14
JESD-609 codee4
length8.65 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.004 A
Humidity sensitivity level1
Number of functions2
Number of entries4
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup11 ns
propagation delay (tpd)16.4 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width3.9 mm
74LVX20
LOW VOLTAGE CMOS DUAL 4-INPUT NAND GATE
WITH 5V TOLERANT INPUTS
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s
s
s
s
s
s
HIGH SPEED:
t
PD
= 4.1ns (TYP.) at V
CC
= 3.3V
5V TOLERANT INPUTS
INPUT VOLTAGE LEVEL:
V
IL
=0.8V, V
IH
=2V at V
CC
=3V
LOW POWER DISSIPATION:
I
CC
= 2
µA
(MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 20
IMPROVED LATCH-UP IMMUNITY
POWER DOWN PROTECTION ON INPUTS
SOP
TSSOP
s)
t(
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVX20MTR
74LVX20TTR
DESCRIPTION
The 74LVX20 is a low voltage CMOS DUAL
4-INPUT NAND GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
The internal circuit is composed of 3 stages
including buffer output, which provides high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
August 2004
Rev. 3
1/11

74LVX20MTR Related Products

74LVX20MTR 74LVX20TTR
Description Logic Gates Dual 4-Input NAND Logic Gates Dual 4-Input NAND
Is it Rohs certified? conform to conform to
Maker STMicroelectronics STMicroelectronics
Parts packaging code SOIC TSSOP
package instruction SOP, SOP14,.25 TSSOP, TSSOP14,.25
Contacts 14 14
Reach Compliance Code compliant compliant
series LV/LV-A/LVX/H LV/LV-A/LVX/H
JESD-30 code R-PDSO-G14 R-PDSO-G14
JESD-609 code e4 e4
length 8.65 mm 5 mm
Load capacitance (CL) 50 pF 50 pF
Logic integrated circuit type NAND GATE NAND GATE
MaximumI(ol) 0.004 A 0.004 A
Number of functions 2 2
Number of entries 4 4
Number of terminals 14 14
Maximum operating temperature 125 °C 125 °C
Minimum operating temperature -55 °C -55 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP TSSOP
Encapsulate equivalent code SOP14,.25 TSSOP14,.25
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing TAPE AND REEL TAPE AND REEL
Peak Reflow Temperature (Celsius) 260 NOT SPECIFIED
power supply 3.3 V 3.3 V
Prop。Delay @ Nom-Sup 11 ns 11 ns
propagation delay (tpd) 16.4 ns 16.4 ns
Certification status Not Qualified Not Qualified
Schmitt trigger NO NO
Maximum seat height 1.75 mm 1.2 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V
Minimum supply voltage (Vsup) 2 V 2 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V
surface mount YES YES
technology CMOS CMOS
Temperature level MILITARY MILITARY
Terminal surface Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form GULL WING GULL WING
Terminal pitch 1.27 mm 0.65 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 30 NOT SPECIFIED
width 3.9 mm 4.4 mm
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