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9112BM-17LF

Description
Clock Buffer PC BUFFER
Categorylogic    logic   
File Size122KB,8 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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9112BM-17LF Overview

Clock Buffer PC BUFFER

9112BM-17LF Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeSOIC
package instructionSOP, SOP16,.25
Contacts16
Manufacturer packaging codeDCG16
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys DescriptionSOIC 150 MIL
series9112
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G16
JESD-609 codee3
length9.9 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
MaximumI(ol)0.008 A
Humidity sensitivity level3
Number of functions1
Number of inverted outputs
Number of terminals16
Actual output times8
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
power supply3.3/5 V
propagation delay (tpd)0.7 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.25 ns
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)3.63 V
Minimum supply voltage (Vsup)2.97 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
Integrated
Circuit
Systems, Inc.
ICS9112-17
Low Skew Output Buffer
General Description
The
ICS9112-17
is a high performance, low skew, low jitter
zero delay buffer. It uses a phase lock loop (PLL)
technology to align, in both phase and frequency, the REF
input with the CLKOUT signal. It is designed to distribute
high speed clocks in PC systems operating at speeds
from 25 to 133 MHz.
ICS9112-17
is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to
the input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
The
ICS9112-17
has two banks of four outputs controlled
by two address lines. Depending on the selected address
line, bank B or both banks can be put in a tri-state mode.
In this mode, the PLL is still running and only the output
buffers are put in a high impedance mode. The test mode
shuts off the PLL and connects the input directly to the
output buffers (see table below for functionality).
The
ICS9112-17
comes in a sixteen pin 150 mil SOIC or
16 pin SSOP package. In the absence of REF input, will
be in the power down mode. In this mode, the PLL is turned
off and the output buffers are pulled low. Power down mode
provides the lowest power consumption for a standby
condition.
Features
Zero input - output delay
Frequency range 25 - 133 MHz (3.3V)
High loop filter bandwidth ideal for Spread Spectrum
applications.
Less than 200 ps cycle to cycle Jitter
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 16 pin, 150 mil SSOP & SOIC package
Pin Configuration
Block Diagram
16 pin SSOP & SOIC
Functionality
FS2 FS1
0
0
1
1
0
1
0
1
CLKA
(1, 4)
Driven
CLKB
(1, 4)
Tristate
CLKOUT
Driven
Driven
PLL
Bypass
Mode
Driven
Output
Source
PLL
PLL
REF
PLL
PLL
Shutdown
N
N
Y
N
Tristate Tristate
PLL
PLL
Bypass Bypass
Mode
Mode
Driven
Driven
0051K—11/02/04

9112BM-17LF Related Products

9112BM-17LF 9112AF-17LFT 9112BM-17LFT
Description Clock Buffer PC BUFFER Clock Buffer PC BUFFER Clock Buffer PC BUFFER
Brand Name Integrated Device Technology Integrated Device Technology -
Is it lead-free? Lead free Lead free -
Is it Rohs certified? conform to conform to -
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) -
Parts packaging code SOIC QSOP -
package instruction SOP, SOP16,.25 SSOP, SSOP16,.25 -
Contacts 16 16 -
Manufacturer packaging code DCG16 PCG16 -
Reach Compliance Code compliant compliant -
ECCN code EAR99 EAR99 -
series 9112 9112 -
Input adjustment STANDARD STANDARD -
JESD-30 code R-PDSO-G16 R-PDSO-G16 -
JESD-609 code e3 e3 -
length 9.9 mm 4.9 mm -
Logic integrated circuit type LOW SKEW CLOCK DRIVER PLL BASED CLOCK DRIVER -
MaximumI(ol) 0.008 A 0.008 A -
Humidity sensitivity level 3 1 -
Number of functions 1 1 -
Number of terminals 16 16 -
Actual output times 8 8 -
Maximum operating temperature 70 °C 70 °C -
Output characteristics 3-STATE 3-STATE -
Package body material PLASTIC/EPOXY PLASTIC/EPOXY -
encapsulated code SOP SSOP -
Encapsulate equivalent code SOP16,.25 SSOP16,.25 -
Package shape RECTANGULAR RECTANGULAR -
Package form SMALL OUTLINE SMALL OUTLINE, SHRINK PITCH -
Peak Reflow Temperature (Celsius) 260 260 -
power supply 3.3/5 V 3.3/5 V -
propagation delay (tpd) 0.7 ns 0.7 ns -
Certification status Not Qualified Not Qualified -
Same Edge Skew-Max(tskwd) 0.25 ns 0.25 ns -
Maximum seat height 1.75 mm 1.75 mm -
Maximum supply voltage (Vsup) 3.63 V 3.63 V -
Minimum supply voltage (Vsup) 2.97 V 2.97 V -
Nominal supply voltage (Vsup) 3.3 V 3.3 V -
surface mount YES YES -
Temperature level COMMERCIAL COMMERCIAL -
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed -
Terminal form GULL WING GULL WING -
Terminal pitch 1.27 mm 0.635 mm -
Terminal location DUAL DUAL -
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED -
width 3.9 mm 3.9 mm -
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