MB3793-34A
Power-Voltage Monitoring IC
with Watchdog Timer
Description
The MB3793 is an integrated circuit to monitor power voltage; it incorporates a watchdog timer.
A reset signal is output when the power is cut or falls abruptly. When the power recovers normally after resetting, a power-on reset
signal is output to microprocessor units (MPUs). An internal watchdog timer with two inputs for system operation diagnosis can provide
a fail-safe function for various application systems.
Model No.
MB3793-34A
Marking Code
3793AJ
Detection voltage
3.4 V
Features
■
■
■
■
■
■
Precise detection of power voltage fall:
±
2.5 %
Detection voltage with hysteresis
Low power dispersion: I
CC
= 38
μA
(Typ)
Internal dual-input watchdog timer
Watchdog timer halt function
Independently-set watchdog and reset times
Application
Arcade Amusement etc.
Cypress Semiconductor Corporation
Document Number: 002-08556 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 20, 2017
MB3793-34A
Contents
Description ................................................................... 1
Features ....................................................................... 1
Application ................................................................... 1
1. Pin Assignment ...................................................... 3
2. Pin Description ....................................................... 3
3. Block Diagram ........................................................ 4
4. Block Functions ..................................................... 5
5. Absolute Maximum Ratings .................................. 6
6. Recommended Operating Conditions .................. 6
7. Electrical Characteristics ...................................... 7
7.1 DC Characteristics ........................................... 7
7.2 AC Characteristics ........................................... 8
8. Timing Diagram ...................................................... 9
8.1 Basic Operation (Positive clock pulse) ............. 9
8.2 Basic Operation (Negative clock pulse) ......... 10
8.3 Single-clock Input Monitoring (Positive Clock
Pulse) .................................................................... 11
8.4 Inhibition Operation (Positive Clock Pulse) .... 12
8.5 Clock Pulse Input Supplementation (Positive
Clock Pulse) .......................................................... 13
9. Operation Sequence ............................................ 14
9.1 Positive Clock Pulse Input ............................. 14
9.2 Negative Clock Pulse Input ............................ 14
9.3 Single-clock Input Monitoring ......................... 14
9.4 Description of Operations .............................. 14
10. Typical Characteristics ...................................... 16
11. Application Example .......................................... 19
11.1 Supply Voltage Monitor and Watchdog
Timer ..................................................................... 19
11.2 Supply Voltage Monitor and Watchdog
Timer Stop ............................................................. 20
11.3 Setting of Compulsory Reset ...................... 20
12. Usage Precaution ............................................... 21
13. Ordering Information ......................................... 21
14. RoHS Compliance Information ......................... 21
15. Package Dimensions ......................................... 22
Document History ..................................................... 23
Sales, Solutions, and Legal Information ................. 24
Document Number: 002-08556 Rev. *C
Page 2 of 24
MB3793-34A
4. Block Functions
1. Comp.S
Comp.S is a comparator with hysteresis to compare the reference voltage with a voltage (V
S
) that is the result of dividing the power
voltage (V
CC
) by resistors R
1
and R
2
. When V
S
falls below 1.24 V, a reset signal is output. This function enables the MB3793 to
detect an abnormality within 1
μs
when the power is cut or falls abruptly.
2. Output circuit
The output circuit has a comparator to control the reset signal (RESET) output. When the voltage at the CTP pin for setting the
power-on reset hold time exceeds the threshold voltage, resetting is canceled.
Since the reset (RESET) output buffer has the CMOS organization, no pull-up resistor is needed.
3. Pulse generator
The pulse generator generates pulses when the voltage at the CK1 and CK2 input clock pins changes from Low level to High level
(positive-edge trigger) and exceeds the threshold voltage; it sends the clock signal to the watchdog timer.
4. Watchdog timer
The watchdog timer can monitor two clock pulses. Short-circuit the CK1 and CK2 clock pins to monitor a single clock pulse.
5. Logic circuit
Logic circuit controls charging and discharging of the power-on reset hold time setting capacity (C
TP
) on a signal of Comp.S and
Watchdog timer.
Document Number: 002-08556 Rev. *C
Page 5 of 24
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