a
FEATURES
Complete Monolithic 12-Bit A/D Converters with
Reference, Clock, and Three-State Output Buffers
Industry Standard Pinout
High Speed Upgrades for AD574A
8- and 16-Bit Microprocessor Interface
8 s (Max) Conversion Time (AD774B)
15 s (Max) Conversion Time (AD674B)
5 V, 10 V, 0 V–10 V, 0 V–20 V Input Ranges
Commercial, Industrial, and Military Temperature
Range Grades
MIL-STD-883-Compliant Versions Available
5V SUPPLY
V
LOGIC
DATA MODE SELECT
12/8
CHIP SELECT
CS
BYTE ADDRESS/
SHORT CYCLE A
0
READ/CONVERT R/C
CHIP ENABLE
CE
12V/15V SUPPLY
V
CC
10V REFERENCE
REF OUT
ANALOG COMMON
AC
REFERENCE INPUT
REF IN
–12V/–15V SUPPLY
V
EE
BIPOLAR OFFSET
BIPOFF
10V SPAN INPUT
10V
IN
20V SPAN INPUT
20V
IN
1
2
3
4
5
6
Complete 12-Bit
A/D Converters
AD674B /AD774B
FUNCTIONAL BLOCK DIAGRAM
28
MSB
N
Y
3 B
B
S L
T E
SAR
COMP
I DAC
O
U
T
P
U
T
B
U
F
F
E
R
S
12
A
T
E
A
N
Y
B
B
L
E
B
N
Y
B
B
L
E
STATUS
STS
27
DB11 (MSB)
26
DB10
25
DB9
24
DB8
23
DB7
22
DB6
21
DB5
20
DB4
19
DB3
18
DB2
17
DB1
16
DB0 (LSB)
15
CONTROL
CLOCK
–
7
8
9
10
+
10V
REF
+
DIGITAL
DATA
OUTPUTS
I REF
199.95
k
11
12
13
14
VOLTAGE
DIVIDER
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD674B and AD774B are complete 12-bit successive-
approximation analog-to-digital converters with three-state
output buffer circuitry for direct interface to 8- and 16-bit
microprocessor busses. A high-precision voltage reference and
clock are included on chip, and the circuit requires only power
supplies and control signals for operation.
The AD674B and AD774B are pin-compatible with the indus-
try standard AD574A, but offer faster conversion time and bus-
access speed than the AD574A and lower power consumption.
The AD674B converts in 15
µs
(maximum) and the AD774B
converts in 8
µs
(maximum).
The monolithic design is implemented using Analog Devices’
BiMOS II process allowing high-performance bipolar analog
circuitry to be combined on the same die with digital CMOS logic.
Offset, linearity, and scaling errors are minimized by active
laser trimming of thin-film resistors.
Five different grades are available. The J and K grades are
specified for operation over the 0°C to 70°C temperature range.
The A and B grades are specified from –40°C to +85°C, the T grade
is specified from –55°C to +125°C. The J and K grades are
available in a 28-lead plastic DIP or 28-lead SOIC. All other grades
are available in a 28-lead hermetically sealed ceramic DIP.
1. Industry Standard Pinout: The AD674B and AD774B use
the pinout established by the industry standard AD574A.
2. Analog Operation: The precision, laser-trimmed scaling and
bipolar offset resistors provide four calibrated ranges: 0 V to
10 V and 0 V to 20 V unipolar; –5 V to +5 V and –10 V to
+10 V bipolar. The AD674B and AD774B operate on +5 V
and
±
12 V or
±
15 V power supplies.
3. Flexible Digital Interface: On-chip multiple-mode three-state
output buffers and interface logic allow direct connection to
most microprocessors. The 12 bits of output data can be
read either as one 12-bit word or as two 8-bit bytes (one with
8 data bits, the other with 4 data bits and 4 trailing zeros).
4. The internal reference is trimmed to 10.00 V with 1% maxi-
mum error and 10 ppm/°C typical temperature coefficient.
The reference is available externally and can drive up to
2.0 mA beyond the requirements of the converter and bipo-
lar offset resistors.
5. The AD674B and AD774B are available in versions compli-
ant with MIL-STD-883. Refer to the Analog Devices Mili-
tary Products Databook or current AD674B/AD774B/883B
data sheet for detailed specifications.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
–
DAC
N
V
EE
C
LSB
AD674B/AD774B
DIGITAL
COMMON DC
to
AD674B/AD774B–SPECIFICATIONS
(Tnoted.)T
V
= +5 V 10%, V = –15 V 10% or –12 V 5%, unless otherwise
MIN
LOGIC
EE
MAX
with V
CC
= +15 V
B Grade
Min Typ Max
12
1/2
1/2
10% or +12 V
T Grade
Min Typ Max
12
1/2
1
5%,
Model (AD674B or AD774B)
RESOLUTION
LINEARITY ERROR @ 25°C
T
MIN
to T
MAX
DIFFERENTIAL LINEARITY ERROR
(Minimum Resolution for Which No
Missing Codes are Guaranteed)
UNIPOLAR OFFSET
1
@ 25°C
BIPOLAR OFFSET
1
@ 25°C
FULL-SCALE CALIBRATION ERROR
1, 2
@ 25°C (with Fixed 50
Ω
Resistor
from REF OUT to REF IN)
TEMPERATURE RANGE
TEMPERATURE DRIFT
3
(Using Internal Reference)
Unipolar
Bipolar Offset
Full-Scale Calibration
POWER SUPPLY REJECTION
Max Change in Full-Scale Calibration
V
CC
= +15 V
±
1.5 V or +12 V
±
0.6 V
V
LOGIC
= +5 V
±
0.5 V
V
EE
= –15 V
±
1.5 V or –12 V
±
0.6 V
ANALOG INPUT
Input Ranges
Bipolar
Unipolar
Input Impedance
10 V Span
20 V Span
POWER SUPPLIES
Operating Range
V
LOGIC
V
CC
V
EE
Operating Current
I
LOGIC
I
CC
I
EE
POWER CONSUMPTION
INTERNAL REFERENCE VOLTAGE
Output Current
(Available for External Loads)
(External Load Should Not
Change During the Conversion)
J Grade
K Grade
Min Typ Max Min Typ Max
12
1
1
12
1/2
1/2
A Grade
Min Typ Max
12
1
1
Unit
Bits
LSB
LSB
12
2
6
12
2
3
12
2
6
12
2
3
12
2
3
Bits
LSB
LSB
0.1
0
0.25
70
0
0.1
0.125
70
–40
0.1
0.25
+85
–40
0.1
0.125
+85
–55
0.1
0.125
+125
% of FS
°C
2
2
6
1
1
2
2
2
8
1
1
5
1
2
7
LSB
LSB
LSB
2
1/2
2
1
1/2
1
2
1/2
2
1
1/2
1
1
1/2
1
LSB
LSB
LSB
–5
–10
0
0
3
6
5
10
+5
+10
10
20
7
14
–5
–10
0
0
3
6
5
10
+5
+10
10
20
7
14
–5
–10
0
0
3
6
+5
+10
10
20
5
7
10
14
–5
–10
0
0
3
6
5
10
+5
+10
10
20
7
14
–5
–10
0
0
3
6
5
10
+5
+10
10
20
7
14
V
V
V
V
kΩ
kΩ
4.5
11.4
–16.5
3.5
3.5
10
220
175
9.9
5.5 4.5
16.5 11.4
–11.4 –16.5
7
7
14
375
3.5
3.5
10
5.5
4.5
16.5 11.4
–11.4 –16.5
7
7
14
5.5
16.5
–11.4
3.5
7
3.5
7
10
14
220
375
175
4.5
11.4
–16.5
3.5
3.5
10
5.5
16.5
–11.4
7
7
14
4.5
11.4
–16.5
5.5
16.5
–11.4
3.5
7
3.5
7
10
14
220
375
175
V
V
V
mA
mA
mA
mW
4
mW
5
V
mA
220
375
175
10.0
10.1
2.0
9.9
220
375
175
9.9
10.0
10.1
2.0
9.9
10.0
10.1 9.9
2.0
10.0
10.1
2.0
10.0
10.1
2.0
NOTES
1
Adjustable to zero.
2
Includes internal voltage reference error.
3
Maximum change from 25°C value to the value at T
MIN
or T
MAX
.
4
Tested with REF OUT tied to REF IN through 50
Ω
resistor, V
CC
= +16.5 V, V
EE
= –16.5 V, V
LOGIC
= +5.5 V, and outputs in high-Z mode.
5
Tested with REF OUT tied to REF IN through 50
Ω
resistor, V
CC
= +12 V, V
EE
= –12 V, V
LOGIC
= +5 V, and outputs in high-Z mode.
Specifications subject to change without notice.
Specifications shown in
boldface
are tested on
all
devices at final electrical test at T
MIN
, 25°C, and T
MAX
. Results from those tests are used to calculate outgoing quality levels. All min and
max specifications are guaranteed, although only those shown in boldface are tested.
–2–
REV. C
AD674B/AD774B
DIGITAL SPECIFICATIONS
Parameter
LOGIC INPUTS
High Level Input Voltage
V
IH
V
IL
Low Level Input Voltage
High Level Input Current
I
IH
I
IL
Low Level Input Current
C
IN
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage
V
OH
Low Level Output Voltage
V
OL
High-Z Leakage Current
I
OZ
C
OZ
High-Z Output Capacitance
(For all grades T
MIN
to T
MAX
with V
CC
= +15 V 10% or +12 V 5%, V
LOGIC
= +5 V
V
EE
= –15 V 10% or –12 V 5%, unless otherwise noted.)
Test Conditions
Min
2.0
–0.5
–10
–10
Max
V
LOGIC
+ 0.5
+0.8
+10
+10
10
10%,
Unit
V
V
µA
µA
pF
V
V
µA
pF
V
IN
= V
LOGIC
V
IN
= 0 V
I
OH
= 0.5 mA
I
OL
= 1.6 mA
V
IN
= 0 to V
LOGIC
2.4
–10
0.4
+10
10
SWITCHING SPECIFICATIONS
CONVERTER START TIMING (Figure 1)
(For all grades T
MIN
to T
MAX
with V
CC
= +15 V 10% or +12 V 5%,
V
LOGIC
= +5 V 10%, V
EE
= –15 V 10% or –12 V 5%, unless otherwise noted.)
CE
t
HEC
t
SSC
t
HSC
Parameter
Symbol
J, K, A, B Grades
T Grade
Min Typ Max Min Typ Max Unit
6
9
4
6
50
50
50
50
50
0
50
8
12
5
7.3
10
15
6
8
200
6
9
4
6
50
50
50
50
50
0
50
8
12
5
7.3
10
15
6
8
225
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
CS
t
SRC
t
HRC
Conversion Time
8-Bit Cycle (AD674B) t
C
12-Bit Cycle (AD674B) t
C
8-Bit Cycle (AD774B) t
C
12-Bit Cycle (AD774B) t
C
STS Delay from CE
t
DSC
CE Pulsewidth
t
HEC
CS
to CE Setup
t
SSC
CS
Low During CE High t
HSC
R/C to CE Setup
t
SRC
R/C LOW During CE High t
HRC
A
0
to CE Setup
t
SAC
A
0
Valid During CE High t
HAC
R/C
A
0
t
HAC
t
SAC
STS
t
C
t
DSC
DB11 – DB0
HIGH
IMPEDANCE
Figure 1. Convert Start Timing
CE
t
SSR
CS
t
HSR
READ TIMING—FULL CONTROL MODE (Figure 2)
R/C
t
SRR
t
HRR
Parameter
Access Time
C
L
= 100 pF
Data Valid After CE Low
Output Float Delay
CS
to CE Setup
R/C to CE Setup
A
0
to CE Setup
CS
Valid After CE Low
R/C High After CE Low
A
0
Valid After CE Low
Symbol
t
DD1
t
HD
t
HL
t
SSR
t
SRR
t
SAR
t
HSR
t
HRR
t
HAR
5
J, K, A, B Grades
T Grade
Min Typ Max Min Typ Max Unit
75
25
20
3
150
50
0
50
0
0
50
50
0
50
0
0
50
2
A
0
STS
DB11 – DB0
t
SAR
t
HAR
150
25
15
4
2
75
150
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
HD
HIGH
IMPEDANCE
t
DD
DATA
VALID
HIGH
IMPEDANCE
t
HL
5V
3k
Figure 2. Read Cycle Timing
DB
N
3k
100pF
DB
N
100pF
NOTES
1
t
DD
is measured with the load circuit of Figure 3a and is defined as the time required
for an output to cross 0.4 V or 2.4 V.
2
0°C to T
MAX
.
3
At –40°C.
4
At –55°C.
5
t
HL
is defined as the time required for the data lines to change 0.5 V when loaded with
the circuit of Figure 3b.
Specifications shown in
boldface
are tested on all devices at final electrical test with
worst case supply voltages at T
MIN
, 25°C, and T
MAX
. Results from those tests are used
to calculate outgoing quality levels. All min and max specifications are guaranteed,
although only those shown in boldface are tested.
Specifications subject to change without notice.
HIGH-Z TO LOGIC 1
HIGH-Z TO LOGIC 0
High-Z to Logic 1
High-Z to Logic 0
5V
3k
Figure 3a. Load Circuit for Access Time Test
DB
N
3k
100pF
DB
N
100pF
LOGIC 1 TO HIGH-Z
LOGIC 0 TO HIGH-Z
Logic 1 to High-Z
Logic 0 to High-Z
Figure 3b. Load Circuit for Output Float Delay Test
REV. C
–3–
AD674B/AD774B
TIMING—STAND ALONE MODE (Figures 4a and 4b)
Parameter
Data Access Time
Low R/C Pulsewidth
STS Delay from R/C
Data Valid After R/C Low
STS Delay After Data Valid
High R/C Pulsewidth
Symbol
t
DDR
t
HRL
t
DS
t
HDR
t
HS
t
HRH
J, K, A, B Grades
T Grade
Min Typ Max Min Typ Max Unit
150
50
200
25
30
150
200
600
50
225
25
30 200 600
150
150
ns
ns
ns
ns
ns
ns
R/C
t
HRL
t
DS
STS
t
C
t
HDR
DB11–DB0
DATA
VALID
HIGH–Z
DATA VALID
t
HS
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
V
CC
to Digital Common . . . . . . . . . . . . . . . . . . . 0 to +16.5 V
V
EE
to Digital Common . . . . . . . . . . . . . . . . . . . . 0 to –16.5 V
V
LOGIC
to Digital Common . . . . . . . . . . . . . . . . . . . 0 to +7 V
Analog Common to Digital Common . . . . . . . . . . . . . . .
±
1 V
Digital Inputs to Digital Common . . . –0.5 V to V
LOGIC
+0.5 V
Analog Inputs to Analog Common . . . . . . . . . . . . V
EE
to V
CC
20 V
IN
to Analog Common . . . . . . . . . . . . . . . . . . . . . .
±
24 V
REF OUT . . . . . . . . . . . . . . . . . . Indefinite Short to Common
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to V
CC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 mW
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Flgure 4a. Standalone Mode Timing Low Pulse R/
C
R/C
t
HRH
STS
t
DS
t
C
t
DDR
HIGH–Z
t
HDR
HIGH–Z
DB11–DB0
DATA
VALID
t
HL
Figure 4b. Standalone Mode Timing High Pulse for R/
C
ORDERING GUIDE
Model
l
Temperature
0°C to 70°C
0°C to 70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
0°C to 70°C
0°C to 70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
Conversion
Time (max)
15
µs
15
µs
15
µs
15
µs
15
µs
15
µs
15
µs
8
µs
8
µs
8
µs
8
µs
8
µs
8
µs
8
µs
INL
(T
MIN
to T
MAX
)
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
Package
Description
Plastic DIP
Plastic DIP
Plastic SOIC
Plastic SOIC
Ceramic DIP
Ceramic DIP
Ceramic DIP
Plastic DIP
Plastic DIP
Plastic SOIC
Plastic SOIC
Ceramic DIP
Ceramic DIP
Ceramic DIP
Package
Option
2
N-28
N-28
R-28
R-28
D-28
D-28
D-28
N-28
N-28
R-28
R-28
D-28
D-28
D-28
AD674BJN
AD674BKN
AD674BAR
AD674BBR
AD674BAD
AD674BBD
AD674BTD
AD774BJN
AD774BKN
AD774BAR
AD774BBR
AD774BAD
AD774BBD
AD774BTD
NOTES
1
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military
Products Databook or the current AD674B/ AD774B/883B data sheet.
2
N = Plastic DIP; D = Hermetic DIP; R = Plastic SOIC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD674B/AD774B features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. C
AD674B/AD774B
DEFINITION OF SPECIFICATIONS
Linearity Error
Quantization Uncertainty
Linearity error refers to the deviation of each individual code
from a line drawn from “zero” through “full scale.” The point
used as “zero” occurs 1/2 LSB (1.22 mV for 10 V span) before
the first code transition (all zeroes to only the LSB “on”). “Full
scale” is defined as a level 1 1/2 LSB beyond the last code tran-
sition (to all ones). The deviation of a code from the true straight
line is measured from the middle of each particular code.
The K, B, and T grades are guaranteed for maximum nonlinear-
ity of
±
1/2 LSB. For these grades, this means that an analog
value that falls exactly in the center of a given code width will
result in the correct digital output code. Values nearer the upper
or lower transition of the code width may produce the next upper
or lower digital output code. The J and A grades are guaranteed
to
±
1 LSB max error. For these grades, an analog value that
falls within a given code width will result in either the correct
code for that region or either adjacent one.
Note that the linearity error is not user adjustable.
Differential Linearity Error (No Missing Codes)
Analog-to-digital converters exhibit an inherent quantization
uncertainty of
±
1/2 LSB. This uncertainty is a fundamental
characteristic of the quantization process and cannot be reduced
for a converter of given resolution.
Left-Justified Data
The output data format is left-justified. This means that the
data represents the analog input as a fraction of full scale, rang-
ing from 0 to 4095/4096. This implies a binary point 4095 to
the left of the MSB.
Full-Scale Calibration Error
A specification that guarantees no missing codes requires that
every code combination appear in a monotonic increasing sequence
as the analog input level is increased. Thus every code must have a
finite width. The AD674B and AD774B guarantee no missing codes
to 12-bit resolution, requiring that all 4096 codes must be present
over the entire operating temperature ranges.
Unipolar Offset
The last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 1 1/2 LSB below the nominal
full scale (9.9963 V for 10.000 V full scale). The full-scale cali-
bration error is the deviation of the actual level at the last transi-
tion from the ideal level. This error, which is typically 0.05% to
0.1% of full scale, can be trimmed out as shown in Figures 7
and 8. The full-scale calibration error over temperature is given
with and without the initial error trimmed out. The temperature
coefficients for each grade indicate the maximum change in the
full-scale gain from the initial value using the internal 10 V
reference.
Temperature Drift
The temperature drift for full-scale calibration, unipolar offset,
and bipolar offset specifies the maximum change from the initial
(25°C) value to the value at T
MIN
or T
MAX
.
Power Supply Rejection
The first transition should occur at a level 1/2 LSB above analog
common. Unipolar offset is defined as the deviation of the actual
transition from that point. This offset can be adjusted as discussed
later. The unipolar offset temperature coefficient specifies the
maximum change of the transition point over temperature,
with or without external adjustment.
Bipolar Offset
The standard specifications assume use of +5.00 V and
±
15.00 V
or
±
12.00 V supplies. The only effect of power supply error on
the performance of the device will be a small change in the
full-scale calibration. This will result in a linear change in all
low-order codes. The specifications show the maximum full-
scale change from the initial value with the supplies at the
various limits.
Code Width
In the bipolar mode the major carry transition (0111 1111 1111
to 1000 0000 0000) should occur for an analog value 1/2 LSB
below analog common. The bipolar offset error and temperature
coefficient specify the initial deviation and maximum change in
the error over temperature.
A fundamental quantity for A/D converter specifications is the
code width. This is defined as the range of analog input values for
which a given digital output code will occur. The nominal value
of a code width is equivalent to 1 least significant bit (LSB) of the
full-scale range or 2.44 mV out of 10 V for a 12-bit ADC.
REV. C
–5–
京公网安备 11010802033920号
EEWORLD
