Intel® 82574 GbE Controller Family
Datasheet
Product Features
PCI Express* (PCIe*)
— 64-bit address master support for systems
using more than 4 GB of physical memory
— Programmable host memory receive buffers
(256 bytes to 16 KB)
— Intelligent interrupt generation features to
enhance driver performance
— Descriptor ring management hardware for
transmit and receive software controlled reset
(resets everything except the configuration
space)
— Message Signaled Interrupts (MSI and MSI-X)
— Configurable receive and transmit data FIFO,
programmable in 1 KB increments
High Performance
MAC
— Flow Control Support compliant with the
802.3X Specification
— VLAN support compliant with the 802.1Q
Specification
— MAC Address filters: perfect match unicast
— filters; multicast hash filtering, broadcast filter
— and promiscuous mode
— Statistics for management and RMOM
— MAC loopback
— TCP segmentation capability compatible with
Large Send offloading features
— Support up to 64 KB TCP segmentation (TSO
v2)
— Fragmented UDP checksum offload for packet
reassemble
— IPv4 and IPv6 checksum offload support
(receive, transmit, and large send)
— Split header support
— Receive Side Scaling (RSS) with two hardware
receive queues
— 9 KB jumbo frame support
— 40 KB packet buffer size
Manageability
— NC-SI for remote management core
— SMBus advanced pass through interface
Low Power
PHY
— Compliant with the 1 Gb/s IEEE 802.3 802.3u
802.3ab Specifications
— IEEE 802.3ab auto negotiation support
— Full duplex operation at 10/100/1000 Mb/s
— Magic Packet* wake-up enable with unique
MAC address
— ACPI register set and power down functionality
supporting D0 andD3 states
— Full wake up support (APM and ACPI 2.0)
— Smart power down at S0 no link and Sx no link
— LAN disable function
Technology
— Half duplex at 10/100 Mb/s
— Auto MDI, MDI-X crossover at all speeds
— 9 mm x 9 mm 64-pin QFN package with
Exposed Pad*
— Configurable LED operation for customization
of LED displays
— TimeSync offload compliant with the 802.1as
specification
— Wider operating temperature range; -40 °C to
85 °C (82574IT only)
June 2014
Revision 3.4
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2
Datasheet—82574 GbE Controller
Contents
1.0
Introduction
............................................................................................................ 12
1.1
Scope .............................................................................................................. 12
1.2
Number Conventions ......................................................................................... 12
1.3
Acronyms......................................................................................................... 13
1.4
Reference Documents ........................................................................................ 14
1.5
82574L Architecture Block Diagram ..................................................................... 15
1.6
System Interface............................................................................................... 15
1.7
Features Summary ............................................................................................ 15
1.8
Product Codes................................................................................................... 18
Pin Interface
........................................................................................................... 20
2.1
Pin Assignments................................................................................................ 20
2.2
Pull-Up/Pull-Down Resistors and Strapping Options ................................................ 21
2.3
Signal Type Definition ........................................................................................ 21
2.3.1 PCIe ..................................................................................................... 21
2.3.2 NVM Port............................................................................................... 22
2.3.3 System Management Bus (SMBus) Interface .............................................. 23
2.3.4 NC-SI and Testability .............................................................................. 23
2.3.5 LEDs..................................................................................................... 24
2.3.6 PHY Pins ............................................................................................... 24
2.3.7 Miscellaneous Pin ................................................................................... 25
2.3.8 Power Supplies and Support Pins .............................................................. 26
2.4
Package ........................................................................................................... 27
Interconnects
.......................................................................................................... 28
3.1
PCIe ................................................................................................................ 28
3.1.1 Architecture, Transaction, and Link Layer Properties ................................... 29
3.1.2 General Functionality .............................................................................. 30
3.1.3 Transaction Layer ................................................................................... 30
3.1.4 Flow Control .......................................................................................... 35
3.1.5 Host I/F ................................................................................................ 37
3.1.6 Error Events and Error Reporting .............................................................. 38
3.1.7 Link Layer ............................................................................................. 41
3.1.8 PHY ...................................................................................................... 42
3.1.9 Performance Monitoring .......................................................................... 43
3.2
Ethernet Interface ............................................................................................. 43
3.2.1 MAC/PHY GMII/MII Interface.................................................................... 43
3.2.2 Duplex Operation for Copper PHY/GMII/MII Operation ................................. 44
3.2.3 Auto-Negotiation & Link Setup Features .................................................... 45
3.2.4 Loss of Signal/Link Status Indication ......................................................... 48
3.2.5 10/100 Mb/s Specific Performance Enhancements....................................... 49
3.2.6 Flow Control .......................................................................................... 50
3.3
SPI Non-Volatile Memory Interface ...................................................................... 53
3.3.1 General Overview ................................................................................... 53
3.3.2 Supported NVM Devices .......................................................................... 53
3.3.3 NVM Device Detection ............................................................................. 54
3.3.4 Device Operation with an External EEPROM................................................ 55
3.3.5 Device Operation with Flash..................................................................... 55
3.3.6 Shadow RAM ......................................................................................... 55
3.3.7 NVM Clients and Interfaces ...................................................................... 57
3.3.8 NVM Write and Erase Sequence ................................................................ 58
2.0
3.0
3
82574 GbE Controller—Datasheet
3.4
3.5
System Management Bus (SMBus) ......................................................................
NC-SI..............................................................................................................
3.5.1 Interface Specification ............................................................................
3.5.2 Electrical Characteristics .........................................................................
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4.0
Initialization
...........................................................................................................
4.1
Introduction .....................................................................................................
4.2
Reset Operation................................................................................................
4.3
Power Up.........................................................................................................
4.3.1 Power-Up Sequence ...............................................................................
4.3.2 Timing Diagram .....................................................................................
4.4
Global Reset (PE_RST_N, PCIe In-Band Reset)......................................................
4.4.1 Reset Sequence.....................................................................................
4.4.2 Timing Diagram .....................................................................................
4.5
Timing Parameters............................................................................................
4.5.1 Timing Requirements .............................................................................
4.5.2 MDIO and NVM Semaphore .....................................................................
4.6
Software Initialization Sequence .........................................................................
4.6.1 Interrupts During Initialization.................................................................
4.6.2 Global Reset and General Configuration ....................................................
4.6.3 Link Setup Mechanisms and Control/Status Bit Summary ............................
4.6.4 Initialization of Statistics.........................................................................
4.6.5 Receive Initialization ..............................................................................
4.6.6 Transmit Initialization.............................................................................
Power Management and Delivery
............................................................................
5.1
Assumptions ....................................................................................................
5.2
Power Consumption ..........................................................................................
5.3
Power Delivery .................................................................................................
5.3.1 The 1.9 V dc Rail ...................................................................................
5.3.2 The 1.05 V dc Rail..................................................................................
5.4
Power Management...........................................................................................
5.4.1 82574L Power States .............................................................................
5.4.2 Auxiliary Power Usage ............................................................................
5.4.3 Power Limits by Certain Form Factors .......................................................
5.4.4 Power States.........................................................................................
5.4.5 Timing of Power-State Transitions ............................................................
5.5
Wake Up .........................................................................................................
5.5.1 Advanced Power Management Wake Up ....................................................
5.5.2 PCIe Power Management Wake Up ...........................................................
5.5.3 Wake-Up Packets...................................................................................
5.0
6.0
Non-Volatile Memory (NVM) Map
...........................................................................102
6.1
Basic Configuration Table..................................................................................102
6.1.1 Hardware Accessed Words .....................................................................104
6.1.2 Software Accessed Words ......................................................................117
6.2
Manageability Configuration Words.....................................................................125
6.2.1 SMBus APT Configuration Words .............................................................125
6.2.2 NC-SI Configuration Words ....................................................................127
4
Datasheet—82574 GbE Controller
7.0
Inline Functions
.................................................................................................... 130
7.1
Packet Reception............................................................................................. 130
7.1.1 Packet Address Filtering ........................................................................ 130
7.1.2 Receive Data Storage............................................................................ 131
7.1.3 Legacy Receive Descriptor Format .......................................................... 131
7.1.4 Extended Rx Descriptor ......................................................................... 134
7.1.5 Packet Split Receive Descriptor .............................................................. 140
7.1.6 Receive Descriptor Fetching ................................................................... 143
7.1.7 Receive Descriptor Write Back................................................................ 143
7.1.8 Receive Descriptor Queue Structure ........................................................ 144
7.1.9 Receive Interrupts ................................................................................ 146
7.1.10 Receive Packet Checksum Offloading ...................................................... 149
7.1.11 Multiple Receive Queues and Receive-Side Scaling (RSS) ........................... 151
7.2
Packet Transmission ........................................................................................ 157
7.2.1 Transmit Functionality........................................................................... 157
7.2.2 Transmission Flow Using Simplified Legacy Descriptors.............................. 158
7.2.3 Transmission Process Flow Using Extended Descriptors.............................. 158
7.2.4 Transmit Descriptor Ring Structure ......................................................... 159
7.2.5 Multiple Transmit Queues ...................................................................... 161
7.2.6 Overview of On-Chip Transmit Modes ...................................................... 161
7.2.7 Pipelined Tx Data Read Requests ............................................................ 162
7.2.8 Transmit Interrupts .............................................................................. 163
7.2.9 Transmit Data Storage .......................................................................... 163
7.2.10 Transmit Descriptor Formats .................................................................. 164
7.2.11 Extended Data Descriptor Format ........................................................... 172
7.3
TCP Segmentation ........................................................................................... 176
7.3.1 TCP Segmentation Performance Advantages ............................................ 176
7.3.2 Ethernet Packet Format......................................................................... 176
7.3.3 TCP Segmentation Data Descriptors ........................................................ 177
7.3.4 TCP Segmentation Source Data .............................................................. 178
7.3.5 Hardware Performed Updating for Each Frame ......................................... 178
7.3.6 TCP Segmentation Use of Multiple Data Descriptors .................................. 179
7.4
Interrupts ...................................................................................................... 182
7.4.1 Legacy and MSI Interrupt Modes ............................................................ 182
7.4.2 MSI-X Mode......................................................................................... 182
7.4.3 Registers............................................................................................. 183
7.4.4 Interrupt Moderation............................................................................. 185
7.4.5 Clearing Interrupt Causes ...................................................................... 187
7.5
802.1q VLAN Support ...................................................................................... 188
7.5.1 802.1q VLAN Packet Format................................................................... 188
7.5.2 Transmitting and Receiving 802.1q Packets.............................................. 189
7.5.3 802.1q VLAN Packet Filtering ................................................................. 189
7.6
LED's ............................................................................................................. 190
7.7
Time SYNC (IEEE1588 and 802.1AS).................................................................. 191
7.7.1 Overview............................................................................................. 191
7.7.2 Flow and Hardware/Software Responsibilities ........................................... 192
7.7.3 Hardware Time Sync Elements ............................................................... 194
7.7.4 PTP Packet Structure ............................................................................ 197
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