Signals on NO_, NC_, and COM_ exceeding V+ or GND are clamped by internal diodes. Limit forward-diode current to
maximum current rating.
Note 2:
This device is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device
can be exposed to during board level solder attach and rework. This limit permits only the use of the solder profiles recom-
mended in the industry-standard specification, JEDEC 020A, paragraph 7.6, Table 3 for IR/VPR and Convection reflow. Pre-
heating is required. Hand or wave soldering is not allowed.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—+3V SUPPLY
(V+ = +2.7V to +3.3V, V
IH
= +1.4V, V
IL
= +0.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at +3V and +25°C.)
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FPGA/CPLD
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