82V3285EQG8 datasheet, PDF - EEWORLD Datasheet

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82V3285EQG8: DescriptionClock Generators & Support Products SUPERSET MASTER; CategoryWireless rf/communication Telecom circuit; File Size1MB，147 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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Clock Generators & Support Products SUPERSET MASTER

82V3285EQG8 Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TQFP
Contacts	100
Manufacturer packaging code	EQG100
Reach Compliance Code	compliant
ECCN code	EAR99
Samacsys Description	TQFP 14 X 14 X 1.4 MM WITH EXPOSE
JESD-30 code	S-PQFP-G100
JESD-609 code	e3
Humidity sensitivity level	3
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP100,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK
power supply	3.3 V
Certification status	Not Qualified
Maximum slew rate	528 mA
Nominal supply voltage	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Base Number Matches	1

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WAN PLL

IDT82V3285

Version 1

December 9, 2008

6024 Silver Creek Valley Road, San Jose, CA 95138

Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775

Printed in U.S.A.

Table of Contents

FEATURES .............................................................................................................................................................................. 9

HIGHLIGHTS.................................................................................................................................................................................................... 9

MAIN FEATURES ............................................................................................................................................................................................ 9

OTHER FEATURES ......................................................................................................................................................................................... 9

APPLICATIONS....................................................................................................................................................................... 9

DESCRIPTION....................................................................................................................................................................... 10

FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11

1 PIN ASSIGNMENT ........................................................................................................................................................... 12

2 PIN DESCRIPTION .......................................................................................................................................................... 13

3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 18

RESET ........................................................................................................................................................................................................... 18

MASTER CLOCK .......................................................................................................................................................................................... 18

INPUT CLOCKS & FRAME SYNC SIGNAL ................................................................................................................................................. 19

3.3.1 Input Clocks .................................................................................................................................................................................... 19

3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 19

3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 20

3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 21

3.5.1 Activity Monitoring ......................................................................................................................................................................... 21

3.5.2 Frequency Monitoring ................................................................................................................................................................... 22

3.6 T0 / T4 DPLL INPUT CLOCK SELECTION .................................................................................................................................................. 23

3.6.1 External Fast Selection (T0 only) .................................................................................................................................................. 23

3.6.2 Forced Selection ............................................................................................................................................................................ 24

3.6.3 Automatic Selection ....................................................................................................................................................................... 24

3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 25

3.7.1 T0 / T4 DPLL Locking Detection ................................................................................................................................................... 25

3.7.1.1 Fast Loss .......................................................................................................................................................................... 25

3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 25

3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 25

3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 25

3.7.2 Locking Status ............................................................................................................................................................................... 25

3.7.3 Phase Lock Alarm (T0 only) .......................................................................................................................................................... 26

3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 27

3.8.1 Input Clock Validity ........................................................................................................................................................................ 27

3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 27

3.8.2.1 Revertive Switch ............................................................................................................................................................... 27

3.8.2.2 Non-Revertive Switch (T0 only) ........................................................................................................................................ 28

3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 28

3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 29

3.9.1 T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 29

3.9.2 T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 31

3.10 T0 / T4 DPLL OPERATING MODE ............................................................................................................................................................... 32

3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 32

3.10.1.1 Free-Run Mode ................................................................................................................................................................ 32

3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 32

3.10.1.3 Locked Mode .................................................................................................................................................................... 32

3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 32

3.1

3.2

3.3

Table of Contents

December 9, 2008

IDT82V3285

WAN PLL

3.11

3.12

3.13

3.14

3.15

3.16

3.17

4.1

5.1

5.2

5.3

5.4

5.5

3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 32

3.10.1.5 Holdover Mode ................................................................................................................................................................. 32

3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 33

3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 33

3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 33

3.10.1.5.4 Manual ........................................................................................................................................................... 33

3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 33

3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 33

3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 33

3.10.2.1 Free-Run Mode ................................................................................................................................................................ 33

3.10.2.2 Locked Mode .................................................................................................................................................................... 33

3.10.2.3 Holdover Mode ................................................................................................................................................................. 33

T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 35

3.11.1 PFD Output Limit ............................................................................................................................................................................ 35

3.11.2 Frequency Offset Limit .................................................................................................................................................................. 35

3.11.3 PBO (T0 only) ................................................................................................................................................................................. 35

3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 35

3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 35

3.11.5.1 T0 Path ............................................................................................................................................................................. 35

3.11.5.2 T4 Path ............................................................................................................................................................................. 36

T0 / T4 APLL ................................................................................................................................................................................................. 37

OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 37

3.13.1 Output Clocks ................................................................................................................................................................................. 37

3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 39

MASTER / SLAVE CONFIGURATION ......................................................................................................................................................... 41

INTERRUPT SUMMARY ............................................................................................................................................................................... 42

T0 AND T4 SUMMARY ................................................................................................................................................................................. 42

POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 43

MASTER / SLAVE APPLICATION ............................................................................................................................................................... 44

4 TYPICAL APPLICATION ................................................................................................................................................. 44

5 MICROPROCESSOR INTERFACE .................................................................................................................................. 45

EPROM MODE .............................................................................................................................................................................................. 46

MULTIPLEXED MODE .................................................................................................................................................................................. 47

INTEL MODE ................................................................................................................................................................................................. 49

MOTOROLA MODE ...................................................................................................................................................................................... 51

SERIAL MODE .............................................................................................................................................................................................. 53

6 JTAG ................................................................................................................................................................................ 55

7 PROGRAMMING INFORMATION .................................................................................................................................... 56

7.1

7.2

REGISTER MAP ............................................................................................................................................................................................ 56

REGISTER DESCRIPTION ........................................................................................................................................................................... 61

7.2.1 Global Control Registers ............................................................................................................................................................... 61

7.2.2 Interrupt Registers ......................................................................................................................................................................... 70

7.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 74

7.2.4 Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 85

7.2.5 T0 / T4 DPLL Input Clock Selection Registers ............................................................................................................................. 96

7.2.6 T0 / T4 DPLL State Machine Control Registers ......................................................................................................................... 101

7.2.7 T0 / T4 DPLL & APLL Configuration Registers .......................................................................................................................... 103

7.2.8 Output Configuration Registers .................................................................................................................................................. 117

7.2.9 PBO & Phase Offset Control Registers ...................................................................................................................................... 124

7.2.10 Synchronization Configuration Registers ................................................................................................................................. 126

JUNCTION TEMPERATURE ...................................................................................................................................................................... 127

EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 127

8 THERMAL MANAGEMENT ........................................................................................................................................... 127

8.1

8.2

Table of Contents

December 9, 2008

IDT82V3285

WAN PLL

9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 129

9.1

9.2

9.3

ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 129

RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 129

I/O SPECIFICATIONS ................................................................................................................................................................................. 130

9.3.1 CMOS Input / Output Port ............................................................................................................................................................ 130

9.3.2 PECL / LVDS Input / Output Port ................................................................................................................................................ 131

9.3.2.1 PECL Input / Output Port ................................................................................................................................................ 131

9.3.2.2 LVDS Input / Output Port ................................................................................................................................................ 133

JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 134

OUTPUT WANDER GENERATION ............................................................................................................................................................ 137

INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 138

OUTPUT CLOCK TIMING ........................................................................................................................................................................... 139

8.3

8.4

HEATSINK EVALUATION .......................................................................................................................................................................... 127

TQFP EPAD THERMAL RELEASE PATH ................................................................................................................................................. 128

9.4

9.5

9.6

9.7

PACKAGE DIMENSIONS.................................................................................................................................................... 144

ORDERING INFORMATION................................................................................................................................................ 147

Table of Contents

December 9, 2008

82V3285EQG8 Related Products

	82V3285EQG8	82V3285EQG
Description	Clock Generators & Support Products SUPERSET MASTER	Clock Generators & Support Products SUPERSET MASTER
Brand Name	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	TQFP	TQFP
Contacts	100	100
Manufacturer packaging code	EQG100	EQG100
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
Samacsys Description	TQFP 14 X 14 X 1.4 MM WITH EXPOSE	TQFP 14 X 14 X 1.4 MM WITH EXPOSE
JESD-30 code	S-PQFP-G100	S-PQFP-G100
JESD-609 code	e3	e3
Humidity sensitivity level	3	3
Number of terminals	100	100
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QFP	HLFQFP
Encapsulate equivalent code	QFP100,.63SQ,20	QFP100,.63SQ,20
Package shape	SQUARE	SQUARE
Package form	FLATPACK	FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH
power supply	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified
Maximum slew rate	528 mA	0.528 mA
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Base Number Matches	1	1

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