2.5 V to 5.5 V, 250 μA, 2-Wire Interface,
Dual Voltage Output, 8-/10-/12-Bit DACs
AD5337/AD5338/AD5339
FEATURES
AD5337
2 buffered 8-bit DACs in 8-lead MSOP
AD5338, AD5338-1
2 buffered 10-bit DACs in 8-lead MSOP
AD5339
2 buffered 12-bit DACs in 8-lead MSOP
Low power operation: 250 μA @ 3 V, 300 μA @ 5 V
2-wire (I
2
C-compatible) serial interface
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 80 nA @ 3 V, 200 nA @ 5 V
3 power-down modes
Double-buffered input logic
Output range: 0 V to V
REF
Power-on reset to 0 V
Simultaneous update of outputs (LDAC function)
Software clear facility
Data readback facility
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +105°C
GENERAL DESCRIPTION
The AD5337/AD5338/AD5339 are dual 8-, 10-, and 12-bit
buffered voltage output DACs, respectively. Each part is housed
in an 8-lead MSOP package and operates from a single 2.5 V to
5.5 V supply, consuming 250 μA at 3 V. On-chip output amplifiers
allow rail-to-rail output swing with a slew rate of 0.7 V/μs. A 2-
wire serial interface operates at clock rates up to 400 kHz. This
interface is SMBus compatible at V
DD
< 3.6 V. Multiple devices
can be placed on the same bus.
The references for the two DACs are derived from one reference
pin. The outputs of all DACs can be updated simultaneously
using the software LDAC function. The parts incorporate a
power-on reset circuit to ensure that the DAC outputs power up
to 0 V and remain there until a valid write to the device takes
place. A software clear function resets all input and DAC
registers to 0 V. A power-down feature reduces the current
consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equip-
ment. The power consumption is typically 1.5 mW at 5 V and
0.75 mW at 3 V, reducing to 1 μW in power-down mode.
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
FUNCTIONAL BLOCK DIAGRAM
V
DD
LDAC
REFIN
SCL
SDA
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
V
OUT
A
A0
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
V
OUT
B
POWER-DOWN
LOGIC
03756-001
POWER-ON
RESET
AD5337/AD5338/AD5339
GND
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.
AD5337/AD5338/AD5339
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 15
Digital-to-Analog Converter Section ...................................... 15
Resistor String ............................................................................. 15
DAC Reference Inputs ............................................................... 15
Output Amplifier........................................................................ 15
Power-on Reset ........................................................................... 15
Serial Interface ............................................................................ 16
Write Operation.......................................................................... 17
Read Operation........................................................................... 18
Double-Buffered Interface ........................................................ 19
Power-Down Modes .................................................................. 19
Applications..................................................................................... 20
Typical Application Circuit....................................................... 20
Bipolar Operation....................................................................... 20
Multiple Devices on One Bus ................................................... 20
Product as a Digitally Programmable Window Detector ..... 21
Coarse and Fine Adjustment Capabilities............................... 21
Power Supply Decoupling ......................................................... 21
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
9/07—Rev. B to Rev. C
Changes to Features.......................................................................... 1
Changes to Table 4............................................................................ 7
Changes to Ordering Guide .......................................................... 25
9/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Figure 31...................................................................... 16
Changes to Table 6.......................................................................... 16
Changes to Table 10........................................................................ 23
Changes to Ordering Guide .......................................................... 25
10/04—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Added AD5338-1................................................................Universal
Changes to Specifications.................................................................4
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide .......................................................... 24
11/03—Rev. 0: Initial Version
Rev. C | Page 2 of 28
AD5337/AD5338/AD5339
SPECIFICATIONS
V
DD
= 2.5 V to 5.5 V; V
REF
= 2 V; R
L
= 2 kΩ to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
2
DC PERFORMANCE
3, 4
AD5337
Resolution
Relative Accuracy
Differential Nonlinearity
AD5338
Resolution
Relative Accuracy
Differential Nonlinearity
AD5339
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband
Min
A Grade
1
Typ
Max
Min
B Grade
1
Typ
Max
Unit
Conditions/Comments
8
±0.15
±0.02
±1
±0.25
8
±0.15
±0.02
±0.5
±0.25
Bits
LSB
LSB
Guaranteed monotonic by
design over all codes
10
±0.5
±0.05
±4
±0.5
10
±0.5
±0.05
±2
±0.50
Bits
LSB
LSB
Guaranteed monotonic by
design over all codes
12
±2
±0.2
±0.4
±0.15
20
±16
±1
±3
±1
60
12
±2
±0.2
±0.4
±0.15
20
±8
±1
±3
±1
60
Bits
LSB
LSB
% of FSR
% of FSR
mV
Guaranteed monotonic by
design over all codes
Lower deadband exists
only if offset error is
negative
Offset Error Drift
5
Gain Error Drift
5
Power Supply Rejection Ratio
5
DC Crosstalk
5
DAC REFERENCE INPUTS
5
V
REF
Input Range
V
REF
Input Impedance
Reference Feedthrough
OUTPUT CHARACTERISTICS
5
Minimum Output Voltage
6
−12
−5
−60
200
0.25
37
V
DD
45
>10
−90
0.001
0.25
37
−12
−5
−60
200
V
DD
45
>10
−90
0.001
ppm of
FSR/°C
ppm of
FSR/°C
dB
μV
V
kΩ
MΩ
dB
V
∆V
DD
= ±10%
R
L
= 2 kΩ to GND or V
DD
Normal operation
Power-down mode
Frequency = 10 kHz
Measure of the minimum
drive capabilities of the
output amplifier
Measure of the maximum
drive capabilities of the
output amplifier
V
DD
= 5 V
V
DD
= 3 V
Coming out of power-
down mode, V
DD
= 5 V
Coming out of power-
down mode, V
DD
= 3 V
Maximum Output Voltage
6
V
DD
−
0.001
0.5
25
16
2.5
5
V
DD
−
0.001
0.5
25
16
2.5
5
V
DC Output Impedance
Short-Circuit Current
Power-Up Time
Ω
mA
mA
μs
μs
Rev. C | Page 3 of 28
AD5337/AD5338/AD5339
Parameter
2
LOGIC INPUTS (A0)
5
Input Current
Input Low Voltage (V
IL
)
Min
A Grade
1
Typ
Max
±1
0.8
0.6
0.5
2.4
2.1
2.0
3
0.7 ×
V
DD
−0.3
V
DD
+
0.3
+0.3
V
DD
±1
0.7 ×
V
DD
–0.3
2.4
2.1
2.0
3
V
DD
+
0.3
+0.3
V
DD
±1
Min
B Grade
1
Typ
Max
±1
0.8
0.6
0.5
Unit
μA
V
V
V
V
V
V
pF
V
V
μA
V
pF
ns
Conditions/Comments
Input High Voltage (V
IH
)
V
DD
= 5 V ± 10%
V
DD
= 3 V ± 10%
V
DD
= 2.5 V
V
DD
= 5 V ± 10%
V
DD
= 3 V ± 10%
V
DD
= 2.5 V
Pin Capacitance
LOGIC INPUTS (SCL, SDA)
5
Input High Voltage (V
IH
)
Input Low Voltage (V
IL
)
Input Leakage Current (I
IN
)
Input Hysteresis (V
HYST
)
Input Capacitance (C
IN
)
Glitch Rejection
SMBus compatible at
V
DD
< 3.6 V
SMBus compatible at
V
DD
< 3.6 V
0.05 ×
V
DD
8
50
0.05 ×
V
DD
8
50
Input filtering suppresses
noise spikes of less than
50 ns
I
SINK
= 3 mA
I
SINK
= 6 mA
LOGIC OUTPUT (SDA)
5
Output Low Voltage (V
OL
)
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
7
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
I
DD
(Power-Down Mode)
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
1
2
0.4
0.6
±1
8
2.5
300
250
0.2
0.08
5.5
375
350
1.0
1.00
2.5
300
250
0.2
0.08
8
0.4
0.6
±1
V
V
μA
pF
V
5.5
375
350
1.0
1.00
V
IH
= V
DD
and V
IL
= GND
μA
μA
μA
μA
V
IH
= V
DD
and V
IL
= GND
I
DD
= 4 μA (max) during 0
readback on SDA
I
DD
= 1.5 μA (max) during 0
readback on SDA
Temperature range for A Version and B Version: −40°C to +105°C; typical at 25°C.
See the Terminology section for explanations of the specific parameters.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: AD5337 (Code 8 to Code 248), AD5338, AD5338-1 (Code 28 to Code 995), AD5339 (Code 115 to Code 3981).
5
Guaranteed by design and characterization; not production tested.
6
For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, V
REF
= V
DD
and offset plus gain error must be positive.
7
I
DD
specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.
Rev. C | Page 4 of 28
AD5337/AD5338/AD5339
AC CHARACTERISTICS
V
DD
= 2.5 V to 5.5 V; R
L
= 2 kΩ to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
2, 3
Output Voltage Settling Time
AD5337
AD5338
AD5339
Slew Rate
Major Code Transition Glitch Energy
Digital Feedthrough
Digital Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
1
2
A Version and B Version
1
Min
Typ
Max
6
7
8
0.7
12
1
1
3
200
−70
8
9
10
Unit
μs
μs
μs
V/μs
nV-s
nV-s
nV-s
nV-s
kHz
dB
Conditions/Comments
V
REF
= V
DD
= 5 V
1/4 scale to 3/4 scale change (0x40 to 0xC0)
1/4 scale to 3/4 scale change (0x100 to 0x300)
1/4 scale to 3/4 scale change (0x400 to 0xC00)
1 LSB change around major carry
V
REF
= 2 V ± 0.1 V p-p
V
REF
= 2.5 V ± 0.1 V p-p, frequency = 10 kHz
Temperature range for A version and B version: −40°C to +105°C; typical at 25°C.
Guaranteed by design and characterization; not production tested.
3
See the Terminology section for explanations of the specific parameters.
Rev. C | Page 5 of 28
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