Data Sheet
FEATURES
DAC update rate: up to 5.7 GSPS
Direct RF synthesis at 2.85 GSPS data rate
DC to 1.425 GHz in baseband mode
DC to 1.0 GHz in 2× interpolation mode
1.425 GHz to 4.2 GHz in Mix-Mode
Bypassable 2× interpolation
Excellent dynamic performance
Supports DOCSIS 3.0 wideband ACLR/harmonic performance
8 QAM carriers: ACLR > 65 dBc
Industry-leading single/multicarrier IF or RF synthesis
4-carrier W-CDMA ACLR at 2457.6 MSPS
f
OUT
= 900 MHz, ACLR = 71 dBc (baseband mode)
f
OUT
= 2100 MHz, ACLR = 68 dBc (Mix-Mode)
f
OUT
= 2700 MHz, ACLR = 67 dBc (Mix-Mode)
Dual-port LVDS and DHSTL data interface
Up to 1.425 GSPS operation
Source synchronous DDR clocking with parity bit
Low power: 1.0 W at 2.85 GSPS (1.3 W at 5.7 GSPS)
11-/14-Bit, 5.7 GSPS,
RF Digital-to-Analog Converter
AD9119/AD9129
FUNCTIONAL BLOCK DIAGRAM
RESET
IRQ
I250U VREF
AD9129
SDIO
SDO
CS
SCLK
FRM_x
(FRAME/
PARITY)
P0_D[13:0]P,
P0_D[13:0]N
DLL
DCI_x
1.2V
SPI
LVDS DDR
RECEIVER
MIX-
NORMAL MODE
DATA ASSEMBLER
BASEBAND
MODE
DATA
LATCH
4× FIFO
Tx DAC
CORE
IOUTP
IOUTN
2×
P1_D[13:0]P,
P1_D[13:0]N
LVDS DDR
RECEIVER
PLL
DCO_x
CLOCK
DISTRIBUTION
DCR
11149-001
DACCLK_x
Figure 1.
APPLICATIONS
Broadband communications systems
CMTS/VOD
Wireless infrastructure: W-CDMA, LTE, point-to-point
Instrumentation, automatic test equipment (ATE)
Radar, jammers
GENERAL DESCRIPTION
The
AD9119/AD9129
are high performance, 11-/14-bit RF digital-
to-analog converters (DACs) supporting data rates up to 2.85
GSPS. The DAC core is based on a quad-switch architecture that
enables dual-edge clocking operation, effectively increasing the
DAC update rate to 5.7 GSPS when configured for Mix-Mode™
or 2× interpolation. The high dynamic range and bandwidth
enable multicarrier generation up to 4.2 GHz.
In baseband mode, wide bandwidth capability combines with high
dynamic range to support from 1 to 158 contiguous carriers for
CATV infrastructure applications. A choice of two optional 2×
interpolation filters is available to simplify the postreconstruction
filter by effectively increasing the DAC update rate by a factor of 2.
In Mix-Mode operation, the
AD9119/AD9129
can reconstruct
RF carriers in the second and third Nyquist zone while still
maintaining exceptional dynamic range up to 4.2 GHz. The
high performance NMOS DAC core features a quad-switch
architecture that enables industry-leading direct RF synthesis
performance with minimal loss in output power. The output
current can be programmed over a range of 9.5 mA to 34.4 mA.
Rev. B
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Trademarks and registered trademarks are the property of their respective owners.
The
AD9119/AD9129
include several features that may further
simplify system integration. A dual-port, source synchronous
LVDS interface simplifies the data interface to a host FPGA/ASIC.
A differential frame/parity bit is also included to monitor the
integrity of the interface. On-chip delay locked loops (DLLs)
optimize timing between different clock domains.
A serial peripheral interface (SPI) configures the
AD9119/
AD9129
and monitors the status of readback registers. The
AD9119/AD9129
are manufactured on a 0.18 µm CMOS
process and operates from +1.8 V and −1.5 V supplies. It is
supplied in a 160-ball chip scale package ball grid array.
PRODUCT HIGHLIGHTS
1.
2.
3.
High dynamic range and signal reconstruction bandwidth
support RF signal synthesis of up to 4.2 GHz.
Dual-port interface with double data rate (DDR) LVDS
data receivers supports 2850 MSPS maximum conversion rate.
Manufactured on a CMOS process; a proprietary switching
technique enhances dynamic performance.
AD9119/AD9129
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
LVDS Digital Specifications ........................................................ 4
HSTL Digital Specifications ........................................................ 4
Serial Port and CMOS Pin Specifications ................................. 5
AC Specifications.......................................................................... 6
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 12
AD9119 ........................................................................................ 12
AD9129 ........................................................................................ 22
Terminology .................................................................................... 35
Serial Communications Port Overview....................................... 36
Serial Peripheral Interface (SPI) ............................................... 36
General Operation of the SPI.................................................... 36
Instruction Mode (8-Bit Instruction) ...................................... 36
Data Sheet
Serial Peripheral Interface Pin Descriptions .......................... 36
MSB/LSB Transfers .................................................................... 37
Serial Port Configuration .......................................................... 37
Theory of Operation ...................................................................... 38
LVDS Data Port Interface .......................................................... 39
Digital Datapath Description ................................................... 42
Reset ............................................................................................. 47
Interrupt Requests ...................................................................... 47
Interface Timing Validation .......................................................... 48
Sample Error Detection (SED) Operation .............................. 48
SED Example............................................................................... 48
Analog Interface Considerations.................................................. 49
Analog Modes of Operation ..................................................... 49
Clock Input.................................................................................. 50
PLL ............................................................................................... 50
Voltage Reference ....................................................................... 51
Analog Outputs .......................................................................... 51
Start-Up Sequence ...................................................................... 54
Device Configuration Registers.................................................... 55
Device Configuration Register Map ........................................ 55
Device Configuration Register Descriptions .......................... 56
Outline Dimensions ....................................................................... 66
Ordering Guide .......................................................................... 66
REVISION HISTORY
6/2017—Rev. A to Rev. B
Changes to Table 8 ............................................................................ 9
Changes to Table 9 .......................................................................... 11
Changes to Figure 87 ...................................................................... 27
Added Reset Section....................................................................... 47
Changes to Figure 149 .................................................................... 51
Changes to Figure 156 .................................................................... 53
Changes to Bits[2:1] Description, Table 29 ................................. 59
Change to Bit 5 Access, Table 37 .................................................. 61
9/2013—Rev. 0 to Rev. A
Changes to Product Title ............................................................................ 1
Changes to Features Section and General Description Section....... 1
Changes to Table 1 ........................................................................... 3
Changes to Table 2 and Table 3 ....................................................... 4
Changes to Dynamic Performance Parameter, Table 5 ............... 6
Changes to Figure 10 and Figure 13............................................. 13
Changes to Figure 21and Figure 23 .............................................. 15
Changes to Figure 24 and Figure 27............................................. 16
Changes to Figure 35 and Figure 37............................................. 18
Changes to Figure 62, Figure 65, and Figure 67 ......................... 23
Changes to Figure 76 and Figure 79 ............................................ 25
Changes to Figure 84, Figure 85, and Figure 87 ......................... 27
Changes to Figure 90 and Figure 92 ............................................ 28
Changes to Figure 95 and Figure 97 ............................................ 29
Changes to Figure 118 ................................................................... 33
Change to Serial Communications Port Overview Section .......... 36
Changes to Theory of Operation Section.................................... 38
Changes to LVDS Data Port Interface Section ........................... 39
Changes to Multiple DAC Synchronization Section ................. 44
Change to PLL Section .................................................................. 50
Change to Voltage Reference Section .......................................... 51
Change to Register 0x01, Table 16 ............................................... 54
Changes to Table 17 ....................................................................... 55
Changes to Bit 6, Table 37 ............................................................. 61
Changes to Table 49, Table 50, Table 51, and Table 52 .............. 63
Changes to Table 53, Table 54, Table 55, Table 56, and Table 57 ... 64
1/2013—Revision 0: Initial Version
Rev. B | Page 2 of 66
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
VDDA = VDD = 1.8 V, VSSA = −1.5 V, I
OUTFS
= 33 mA, T
A
= −40°C to +85°C.
Table 1.
Parameter
RESOLUTION
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUTS
Gain Error (with Internal Reference)
Full-Scale Output Current Maximum
Full-Scale Output Current Minimum
Output Compliance Range
Output Impedance
1
DAC CLOCK INPUT (DACCLK_P, DACCLK_N)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
TEMPERATURE DRIFT
Gain
Reference Voltage
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
VDDA
FIR40 Enabled, DACCLK > 2600 MSPS
VSSA
DIGITAL SUPPLY VOLTAGES
VDD
FIR40 Enabled, DACCLK > 2600 MSPS
SUPPLY CURRENTS AND POWER DISSIPATION, 2.3 GSPS
(NORMAL MODE)
I
VDDA
I
VSSA
I
DVDD
Power Dissipation
Normal Mode
FIR25 Enabled
FIR40 Enabled
Reduced Power Mode, Power-Down Enabled
(Register 0x01 = 0xEF)
I
VDDA
I
VSSA
I
VDD
SUPPLY CURRENTS AND POWER DISSIPATION, 2.8 GSPS
(NORMAL MODE)
I
VDDA
I
VSSA
I
DVDD
Power Dissipation (Normal Mode)
1
AD9119/AD9129
Min
AD9119
Typ
11
0.2
0.15
+2.5
34.2
9.4
Max
Min
AD9129
Typ
14
1.4
1.1
+2.5
34.2
9.4
Max
Unit
Bits
LSB
LSB
%
mA
mA
V
33.4
9.1
1.5
34.9
9.6
2.5
33.4
9.1
1.5
34.9
9.6
2.5
0.4
1
1.2
60
20
1.0
5
2
0.4
1
1.2
60
20
1.0
5
2
V
V
ppm/°C
ppm/°C
V
kΩ
1.70
1.8
−1.4
1.70
1.8
1.80
1.9
−1.5
1.8
1.9
1.90
2.0
−1.6
1.90
2.0
1.70
1.8
−1.4
1.70
1.8
1.80
1.9
−1.5
1.8
1.9
1.90
2.0
−1.6
1.90
2.0
V
V
V
V
V
202
53
307
1.0
1.17
1.3
209
54
327
1.05
1.24
1.4
202
53
307
1.0
1.17
1.3
209
54
327
1.05
1.24
1.4
mA
mA
mA
W
W
W
7.6
6
0.4
7.6
6
0.4
mA
µA
mA
230
53
336
1.1
230
53
336
1.1
mA
mA
mA
W
For more information about output impedance, see the Output Stage Configuration section.
Rev. B | Page 3 of 66
AD9119/AD9129
LVDS DIGITAL SPECIFICATIONS
Data Sheet
VDDA = VDD = 1.8 V, VSSA = −1.5 V, I
OUTFS
= 33 mA, T
A
= −40°C to +85°C. LVDS drivers and receivers are compatible with the IEEE
Standard 1596.3-1996, unless otherwise noted.
Table 2.
Parameter
LVDS DATA INPUTS (P1_D[13:0]P, P1_D[13:0]N,
P0_D[13:0]P, P0_D[13:0]N, FRM_P, FRM_N)
Input Voltage Range
Input Differential Threshold
Input Differential Hysteresis
Receiver Differential Input Impedance
LVDS Input Rate
Input Capacitance
LVDS CLOCK INPUTS (DCI_P, DCI_N)
Input Voltage Range
Input Differential Threshold
Input Differential Hysteresis
Receiver Differential Input Impedance
Maximum Clock Rate
LVDS CLOCK OUTPUTS (DCO_P, DCO_N)
Output Voltage High
Output Voltage Low
Output Differential Voltage
Output Offset Voltage
Output Impedance, Single-Ended
R
O
Mismatch Between A and B
Change in |V
OD
| Between Setting 0 and Setting 1
Change in V
OS
Between Setting 0 and Setting 1
Output Current
Driver Shorted to Ground
Drivers Shorted Together
Power-Off Output Leakage
Maximum Clock Rate
Symbol
Test Conditions/Comments
Px_DxP = V
IA
, Px_DxN = V
IB
Min
Typ
Max
Unit
V
IA
, V
IB
V
IDTH
V
IDTHH
− V
IDTHL
R
IN
825
−100
20
80
1425
1.2
DCI_P = V
IA
, DCI_N = V
IB
1575
+100
120
mV
mV
mV
Ω
MSPS
pF
mV
mV
mV
Ω
MHz
V
IA
, V
IB
V
IDTH
V
IDTHH
− V
IDTHL
R
IN
DCO_P = V
OA
, DCO_N = V
OB
,
100 Ω termination
V
OA
, V
OB
V
OA
, V
OB
|V
OA
|, |V
OB
|
V
OS
R
O
∆R
O
|∆V
OD
|
∆V
OS
I
SA
, I
SB
I
SAB
|I
XA
|, |I
XB
|
825
−225
20
80
712.5
1575
+225
120
1375
Register 0x7C[7:6] = 01b (default)
1025
200
1150
80
225
100
250
1250
120
10
25
25
20
4
10
712.5
mV
mV
mV
mV
Ω
%
mV
mV
mA
mA
µA
MHz
HSTL DIGITAL SPECIFICATIONS
VDDA = VDD = 1.8 V, VSSA = −1.5 V, I
OUTFS
= 33 mA, T
A
= −40°C to +85°C. HSTL receiver levels are compatible with the EIA/JEDEC
JESD8-6 standard, unless otherwise noted.
Table 3.
Parameter
HSTL DATA INPUTS (P1_D[13:0]P, P1_D[13:0]N,
P0_D[13:0]P, P0_D[13:0]N, FRM_P, FRM_N)
Common-Mode Input Voltage Range
Differential Input Voltage
Receiver Differential Input Impedance
HSTL Input Rate
Input Capacitance
HSTL CLOCK INPUT (DCI_P, DCI_N)
Common-Mode Input Voltage Range
Differential Input Voltage
Receiver Differential Input Impedance
Maximum Clock Rate
Symbol
Test Comments/Conditions
Px_DxP = V
IA
, Px_DxN = V
IB
Min
Typ
Max
Unit
V
IA
, V
IB
R
IN
0.68
200
80
1425
1.2
DCI_P = V
IA
, DCI_N = V
IB
0.9
120
V
mV
Ω
MSPS
pF
mV
mV
Ω
MHz
V
IA
, V
IB
R
IN
Rev. B | Page 4 of 66
0.68
450
80
712.5
0.9
120
Data Sheet
SERIAL PORT AND CMOS PIN SPECIFICATIONS
VDDA = VDD = 1.8 V, VSSA = −1.5 V, I
OUTFS
= 33 mA, T
A
= −40°C to +85°C.
Table 4
.
Parameter
WRITE OPERATION
SCLK Clock Rate
SCLK Clock High
SCLK Clock Low
SDIO to SCLK Setup Time
SCLK to SDIO Hold Time
CS to SCLK Setup Time
SCLK to CS Hold Time
READ OPERATION
SCLK Clock Rate
SCLK Clock High
SCLK Clock Low
SDIO to SCLK Setup Time
SCLK to SDIO Hold Time
CS to SCLK Setup Time
SCLK to SDIO (or SDO) Data Valid Time
CS to SDIO (or SDO) Output Valid to High-Z
INPUTS (SDI, SDIO, SCLK, CS)
Voltage In High
Voltage In Low
Current In High
Current In Low
OUTPUTS (SDIO, SYNC)
Voltage Out High
Voltage Out Low
Current Out High
Current Out Low
Symbol
f
SCLK
, 1/t
SCLK
t
HIGH
t
LOW
t
DS
t
DH
t
S
t
H
See Figure 127
f
SCLK
, 1/t
SCLK
t
HIGH
t
LOW
t
DS
t
DH
t
S
t
DV
t
EZ
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OH
I
OL
Test Comments/Conditions
See Figure 126
Min
Typ
AD9119/AD9129
Max
20
Unit
MHz
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
20
20
10
5
10
5
20
20
20
10
5
10
10
2
1.2
1.8
0
0.4
+75
−150
1.3
0
4
4
2.0
0.3
V
V
µA
µA
V
V
mA
mA
Rev. B | Page 5 of 66
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