BLM7G1822S-20PB;
BLM7G1822S-20PBG
LDMOS 2-stage power MMIC
Rev. 4 — 1 September 2015
Product data sheet
1. Product profile
1.1 General description
The BLM7G1822S-20PB(G) is a dual section, 2-stage power MMIC using Ampleon’s state
of the art GEN7 LDMOS technology. This multiband device is perfectly suited as general
purpose driver or small cell final in the frequency range from 1805 MHz to 2170 MHz.
Available in gull wing or straight lead outline.
Table 1.
Performance
Typical RF performance at T
case
= 25
C; I
Dq1
= 27 mA; I
Dq2
= 76 mA.
Test signal: 3GPP test model 1; 64 DPCH; PAR = 9.9 dB at 0.01% probability on CCDF; per section
unless otherwise specified in a class-AB production circuit.
Test signal
single carrier W-CDMA
f
(MHz)
2167.5
V
DS
(V)
28
P
L(AV)
(W)
2
G
p
(dB)
32.3
D
(%)
23
ACPR
5M
(dBc)
41
1.2 Features and benefits
Designed for broadband operation (frequency 1805 MHz to 2170 MHz)
High section-to-section isolation enabling multiple combinations
Integrated temperature compensated bias
Biasing of individual stages is externally accessible
Integrated ESD protection
Excellent thermal stability
High power gain
On-chip matching for ease of use
Compliant to Directive 2002/95/EC, regarding restriction of hazardous substances
(RoHS)
1.3 Applications
RF power MMIC for multi-carrier and multi-standard GSM, W-CDMA and LTE base
stations in the 1805 MHz to 2170 MHz frequency range. Possible circuit topologies are
the following as also depicted in
Section 8.1:
Dual section or single ended
Doherty
Quadrature combined
Push-pull
BLM7G1822S-20PB(G)
LDMOS 2-stage power MMIC
2. Pinning information
2.1 Pinning
pin 1 index
V
DS(A1)
V
GS(A2)
V
GS(A1)
RF_IN_A
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
RF_IN_B
V
GS(B1)
V
GS(B2)
V
DS(B1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
RF_OUT_A / V
DS(A2)
15
RF_OUT_B / V
DS(B2)
aaa-009322
Transparent top view
The exposed backside of the package is the ground terminal of the device.
Fig 1.
Pin configuration
2.2 Pin description
Table 2.
Symbol
V
DS(A1)
V
GS(A2)
V
GS(A1)
RF_IN_A
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
RF_IN_B
V
GS(B1)
V
GS(B2)
V
DS(B1)
BLM7G1822S-20PB_S-20PBG#4
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
drain-source voltage of driver stage A1
gate-source voltage of final stage A2
gate-source voltage of driver stage A1
RF input section A
not connected
not connected
not connected
not connected
not connected
not connected
RF input section B
gate-source voltage of driver stage B1
gate-source voltage of final stage B2
drain-source voltage of driver stage B1
All information provided in this document is subject to legal disclaimers.
© Ampleon The Netherlands B.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 1 September 2015
2 of 18
BLM7G1822S-20PB(G)
LDMOS 2-stage power MMIC
Table 2.
Symbol
RF_OUT_B/V
DS(B2)
RF_OUT_A/V
DS(A2)
GND
Pin description
…continued
Pin
15
16
flange
Description
RF output section B / drain-source voltage of final stage B2
RF output section A / drain-source voltage of final stage A2
RF ground
3. Ordering information
Table 3.
Ordering information
Package
Name
BLM7G1822S-20PB
BLM7G1822S-20PBG
HSOP16F
HSOP16
Description
plastic, heatsink small outline package; 16 leads(flat)
plastic, heatsink small outline package; 16 leads
Version
SOT1211-2
SOT1212-2
Type number
4. Block diagram
V
DS(A1)
RF_IN_A
RF_OUT_A / V
DS(A2)
V
GS(A1)
V
GS(A2)
TEMPERATURE
COMPENSATED BIAS
V
GS(B1)
V
GS(B2)
TEMPERATURE
COMPENSATED BIAS
RF_IN_B
V
DS(B1)
RF_OUT_B / V
DS(B2)
aaa-009323
Fig 2.
Block diagram
5. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS
T
stg
T
j
T
case
[1]
Parameter
drain-source voltage
gate-source voltage
storage temperature
junction temperature
case temperature
Conditions
Min
-
0.5
65
[1]
Max
65
+13
+150
225
150
Unit
V
V
C
C
C
-
-
Continuous use at maximum temperature will affect the reliability. For details refer to the online MTF
calculator.
BLM7G1822S-20PB_S-20PBG#4
All information provided in this document is subject to legal disclaimers.
© Ampleon The Netherlands B.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 1 September 2015
3 of 18
BLM7G1822S-20PB(G)
LDMOS 2-stage power MMIC
6. Thermal characteristics
Table 5.
Thermal characteristics
Measured for total device.
Symbol
R
th(j-c)
Parameter
thermal resistance from junction to case
Conditions
final stage; T
case
= 90
C;
P
L
= 3.56 W
driver stage; T
case
= 90
C;
P
L
= 3.56 W
[1]
When operated with a CW signal.
[1]
[1]
Value
1.9
6.2
Unit
K/W
K/W
7. Characteristics
Table 6.
DC characteristics
T
case
= 25
C; per section unless otherwise specified.
Symbol
Final stage
V
(BR)DSS
V
GSq
I
Dq
/T
I
DSS
I
DSX
I
GSS
V
(BR)DSS
V
GSq
I
Dq
/T
I
DSS
I
DSX
I
GSS
[1]
[2]
Parameter
drain-source breakdown voltage
gate-source quiescent voltage
quiescent drain current variation with
temperature
drain leakage current
drain cut-off current
gate leakage current
drain-source breakdown voltage
gate-source quiescent voltage
quiescent drain current variation with
temperature
drain leakage current
drain cut-off current
gate leakage current
Conditions
V
GS
= 0 V; I
D
= 150.8
A
V
DS
= 28 V; I
D
= 76 mA
V
DS
= 28 V; I
D
= 76 mA
40 C
T
case
+85
C
V
GS
= 0 V; V
DS
= 28 V
V
GS
= 5.55 V; V
DS
= 10 V
V
GS
= 1.0 V; V
DS
= 0 V
V
GS
= 0 V; I
D
= 30.16
A
V
DS
= 28 V; I
D
= 27 mA
V
DS
= 28 V; I
D
= 27 mA
40 C
T
case
+85
C
V
GS
= 0 V; V
DS
= 28 V
V
GS
= 5.55 V; V
DS
= 10 V
V
GS
= 1.0 V; V
DS
= 0 V
[2]
[2]
[1]
[1]
Min
65
1.5
1.7
-
-
-
-
65
1.6
1.9
-
-
-
-
Typ
-
2
2.65
1
-
2.8
-
-
2.1
2.85
1
-
0.55
-
Max
-
2.5
3.6
-
1.4
-
140
-
2.6
3.8
-
1.4
-
140
Unit
V
V
V
%
A
A
nA
V
V
V
%
A
A
nA
Driver stage
In production circuit with 1105
gate feed resistor.
In production circuit with 765
gate feed resistor.
BLM7G1822S-20PB_S-20PBG#4
All information provided in this document is subject to legal disclaimers.
© Ampleon The Netherlands B.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 1 September 2015
4 of 18
BLM7G1822S-20PB(G)
LDMOS 2-stage power MMIC
Table 7.
RF Characteristics
Typical RF performance at T
case
= 25
C; V
DS
= 28 V; I
Dq1
= 27 mA; I
Dq2
= 76 mA; P
L(AV)
= 2 W. Per section unless otherwise
specified, measured in an Ampleon wideband f = 1807.5 MHz to 2167.5 MHz straight lead production circuit.
Symbol
G
p
D
RL
in
ACPR
5M
PAR
O
I
Dq
/T
Parameter
power gain
drain efficiency
input return loss
adjacent channel power ratio (5 MHz)
output peak-to-average ratio
quiescent drain current variation with
temperature
Conditions
f = 1807.5 MHz
f = 2167.5 MHz
f = 1807.5 MHz
f = 2167.5 MHz
f = 2167.5 MHz
f = 1807.5 MHz
f = 2167.5 MHz
f = 1807.5 MHz
f = 2167.5 MHz
T =
40 C
to +85
C
final stage I
Dq
;
gate feed resistor = 1105
driver stage I
Dq
;
gate feed resistor = 765
Test signal: CW
[2]
s21
s
21
2
[1]
[2]
Min
-
30.8
-
20
-
-
-
-
7.2
-
-
Typ
34
32.3
22
23
19
41
41
8.4
8.4
1
1
Max
-
33.8
-
-
10
-
37
-
-
-
-
Unit
dB
dB
%
%
dB
dBc
dBc
dB
dB
%
%
Test signal: single carrier W-CDMA
[1]
phase response difference
insertion power gain difference
between sections
between sections
10
0.5
-
-
+10
+0.5
deg
dB
3GPP test model 1; 64 DPCH; PAR = 9.9 dB at 0.01% probability on CCDF.
f = 2170 MHz.
8. Application information
Table 8.
Typical performance
Test signal: 1-tone CW; RF performance at T
case
= 25
C; V
DS
= 28 V; I
Dq1
= 45 mA (both sections); I
Dq2
= 140 mA (both
sections) unless otherwise specified, measured in an Ampleon f = 2110 MHz to 2170 MHz straight lead class AB application
circuit (see
Figure 3
for the component layout and
Figure 4
for the electrical schematic).
Symbol
P
L(1dB)
P
L(3dB)
D
G
p
B
video
G
flat
G/T
s
12
2
K
[1]
Parameter
output power at 1 dB gain compression
output power at 3 dB gain compression
drain efficiency
power gain
video bandwidth
gain flatness
gain variation with temperature
isolation
Rollett stability factor
Conditions
f = 2140 MHz
f = 2140 MHz
at P
L(1dB)
; f = 2140 MHz
P
L(AV)
= 1.585 W; f = 2140 MHz
2-tone CW; P
L(AV)
= 1.585 W;
f = 2140 MHz
over a frequency range of 60 MHz;
P
L(AV)
= 1.585 W
f = 2140 MHz
between sections A and B;
P
L(AV)
= 1.585 W; f = 2140 MHz
T =
40 C;
f = 0.1 GHz to 3 GHz
[1]
Min Typ
-
-
-
-
-
-
-
-
-
Max Unit
W
W
%
dB
MHz
dB
dB/C
dB
43.5 -
44.1 -
47.6 -
31.5 -
170
0.4
-
-
0.03 -
28.5 -
>1
-
Measured on dual section evaluation board I
Dq1
= 40 mA (both sections); I
Dq2
= 150 mA (both sections).
All information provided in this document is subject to legal disclaimers.
© Ampleon The Netherlands B.V. 2015. All rights reserved.
BLM7G1822S-20PB_S-20PBG#4
Product data sheet
Rev. 4 — 1 September 2015
5 of 18
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