7-Output 1.8V HCSL Fanout Buffer with
Zo=100ohms
9DBV0741
DATASHEET
Description
The 9DBV0741 is a member of IDT's Full-Featured PCIe
family. The device has 7 output enables for clock
management, and 3 selectable SMBus addresses. It has
integrated terminations for direct connection to 100
transmission lines.
Features/Benefits
•
100 direct connect; saves 28 resistors and 48mm
2
•
•
•
•
•
compared to standard HCSL
41mW typical power consumption; eliminates thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features allow optimization to customer
requirements
•
Slew rate for each output; allows tuning for various line
lengths
•
Differential output amplitude; allows tuning for various
application environments
1MHz to 200MHz operating frequency
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Device contains default configuration; SMBus interface not
required for device operation
40-pin 5 x 5 mm VFQFPN; minimal board space
Recommended Application
PCIe Gen1–3 clock distribution in Storage, Networking,
Compute, Consumer
Output Features
•
7 1–200MHz Low-Power (LP) HCSL DIF pairs with
•
Z
O
=100
Easy AC-coupling to other logic families, see IDT
application note
AN-891
Key Specifications
•
•
•
•
Additive
cycle-to-cycle jitter < 5ps
Output-to-output skew < 60ps
Additive
phase jitter is < 100fs rms for PCIe Gen3
Additive
phase jitter < 300fs rms (12kHz–20MHz at
125MHz)
•
•
•
•
•
Block Diagram
vOE(6:0)#
7
DIF6
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0741 MARCH 10, 2017
1
©2017 Integrated Device Technology, Inc.
9DBV0741 DATASHEET
Pin Configuration
^CKPWRGD_PD#
40 39 38 37 36 35 34 33 32 31
vSADR_tri
1
vOE6#
2
DIF6
3
DIF6#
4
VDDR1.8
5
CLK_IN
6
CLK_IN#
7
GNDDIG
8
SCLK_3.3
9
SDATA_3.3
10
11 12 13 14 15 16 17 18 19 20
VDDDIG1.8
VDD1.8
vOE0#
DIF0
DIF0#
DIF1
VDDIO
VDDIO
DIF1#
NC
30
NC
29
vOE3#
28
DIF3#
VDD1.8
27
DIF3
26
VDDIO
25
VDD1.8
24
vOE2#
23
DIF2#
22
DIF2
21
vOE1#
VDDIO
9DBV0741
connect epad to
GND
40-VFQFPN
^ prefix indicates internal Pull-Up Resistor
v prefix indicates Internal Pull-Dow n Resistor
5mm x 5mm 0.4mm pin pitch
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+
Read/Write bit
x
x
x
Power Management Table
CKPWRGD_PD#
0
1
1
1
CLK_IN
X
Running
Running
Running
SMBus
OEx bit
X
0
1
1
OEx# Pin
X
X
0
1
DIFx
True O/P Comp. O/P
Low
Low
Low
Low
Running
Running
Low
Low
Power Connections
Pin Number
VDD
5
11
16, 25, 31
12,17,26,32,
39
VDDIO
GND
41
8
41
Description
Input
receiver
analog
Digital power
DIF outputs,
logic
7-OUTPUT 1.8V HCSL FANOUT BUFFER WITH ZO=100OHMS
2
VDDIO
vOE5#
vOE4#
DIF5#
DIF4#
DIF5
DIF4
MARCH 10, 2017
9DBV0741 DATASHEET
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
PIN NAME
vSADR_tri
vOE6#
DIF6
DIF6#
VDDR1.8
CLK_IN
CLK_IN#
GNDDIG
SCLK_3.3
SDATA_3.3
VDDDIG1.8
VDDIO
vOE0#
DIF0
DIF0#
VDD1.8
VDDIO
DIF1
DIF1#
NC
vOE1#
DIF2
DIF2#
vOE2#
VDD1.8
VDDIO
DIF3
DIF3#
vOE3#
NC
VDD1.8
VDDIO
DIF4
DIF4#
vOE4#
DIF5
DIF5#
vOE5#
VDDIO
^CKPWRGD_PD#
EPAD
PIN TYPE
DESCRIPTION
Tri-level latch to select SMBus Address. It has an internal 120kohm pull down resistor. See
LATCHED
SMBus Address Selection Table.
IN
Active low input for enabling output 6. This pin has an internal 120kohm pull-down.
IN
1 = disable outputs, 0 = enable outputs.
OUT
Differential true clock output.
OUT
Differential complementary clock output.
Power supply for differential input clock (receiver). This VDD should be treated as an analog
PWR
power rail and filtered appropriately. Nominally 1.8V.
IN
True input for differential reference clock.
IN
Complementary input for differential reference clock.
GND
Ground pin for digital circuitry.
IN
Clock pin of SMBus circuitry, 3.3V tolerant.
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
PWR
1.8V digital power (dirty power).
PWR
Power supply for differential outputs.
Active low input for enabling output 0. This pin has an internal 120kohm pull-down.
IN
1 = disable outputs, 0 = enable outputs.
OUT
Differential true clock output.
OUT
Differential complementary clock output.
PWR
Power supply, nominally 1.8V
PWR
Power supply for differential outputs.
OUT
Differential true clock output.
OUT
Differential complementary clock output.
N/A
No connection.
Active low input for enabling output 1. This pin has an internal 120kohm pull-down.
IN
1 = disable outputs, 0 = enable outputs.
OUT
Differential true clock output.
OUT
Differential complementary clock output.
Active low input for enabling output 2. This pin has an internal 120kohm pull-down.
IN
1 = disable outputs, 0 = enable outputs.
PWR
Power supply, nominally 1.8V
PWR
Power supply for differential outputs.
OUT
Differential true clock output.
OUT
Differential complementary clock output.
Active low input for enabling output 3. This pin has an internal 120kohm pull-down.
IN
1 = disable outputs, 0 = enable outputs.
N/A
No connection.
PWR
Power supply, nominally 1.8V
PWR
Power supply for differential outputs.
OUT
Differential true clock output.
OUT
Differential complementary clock output.
Active low input for enabling output 4. This pin has an internal 120kohm pull-down.
IN
1 = disable outputs, 0 = enable outputs.
OUT
Differential true clock output.
OUT
Differential complementary clock output.
Active low input for enabling output 5. This pin has an internal 120kohm pull-down.
IN
1 = disable outputs, 0 = enable outputs.
PWR
Power supply for differential outputs.
Input notifies device to sample latched inputs and start up on first high assertion. Low enters
IN
Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal
120kohm pull-up resistor.
GND
Connect paddle to ground.
MARCH 10, 2017
3
7-OUTPUT 1.8V HCSL FANOUT BUFFER WITH ZO=100OHMS
9DBV0741 DATASHEET
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs
Zo=100W
2pF
2pF
Rs
Device
Alternate Terminations
The 9DBV0741 can easily drive LVPECL, LVDS, and CML logic. See
“AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's
“Universal” Low-Power HCSL Outputs”
for details.
7-OUTPUT 1.8V HCSL FANOUT BUFFER WITH ZO=100OHMS
4
MARCH 10, 2017
9DBV0741 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV0741. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
Supply Voltage
Input Voltage
Input High Voltage, SMBus
Storage Temperature
Junction Temperature
Input ESD Protection
1
2
SYMBOL
VDDx
V
IN
V
IHSMB
Ts
Tj
ESD prot
CONDITIONS
Applies to VDD, VDDA and VDDIO
SMBus clock and data pins
MIN
-0.5
-0.5
-65
TYP
MAX
2.5
V
DD
+0.5
3.6
150
125
UNITS NOTES
V
V
V
°C
°C
V
1,2
1,3
1
1
1
1
Human Body Model
2000
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.5V.
Electrical Characteristics–Clock Input Parameters
TA = T
COM
or T
IND
; Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER
Input Crossover Voltage -
DIF_IN
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
Input Jitter - Cycle to Cycle
1
2
SYMBOL
V
CROSS
V
SWING
dv/dt
I
IN
d
tin
J
DIFIn
CONDITIONS
Cross over voltage
Differential value
Measured differentially
V
IN
= V
DD ,
V
IN
= GND
Measurement from differential waveform
Differential measurement
MIN
150
300
0.4
-5
40
0
TYP
MAX
900
UNITS NOTES
mV
mV
1
1
1,2
1
1
8
5
60
125
V/ns
µA
%
ps
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through +/-75mV window centered around differential zero.
MARCH 10, 2017
5
7-OUTPUT 1.8V HCSL FANOUT BUFFER WITH ZO=100OHMS
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