Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications supporting DDR 200/266/300/333
PIN CONFIGURATION
GND 1
Y
0
2
Y
0
3
V
DDQ
4
Y
1
5
Y
1
6
GND 7
GND 8
Y
2
9
Y
2
10
V
DDQ
11
SCL 12
CLK 13
CLK 14
V
DD
I
2
C 15
AV
DD
16
AGND 17
GND 18
Y
3
19
Y
3
20
V
DDQ
21
48 GND
47 Y
5
46 Y
5
45 V
DDQ
44 Y
6
43 Y
6
42 GND
41 GND
40 Y
7
39 Y
7
38 V
DDQ
37 SDA
36 FBIN
35 FBIN
34 V
DDQ
33 FBOUT
32 FBOUT
31 GND
30 Y
8
29 Y
8
28 V
DDQ
27 Y
9
26 Y
9
25 GND
•
Full DDR solution provided when used with PCK2002P or
PCK2002PL, and PCK2022RA
•
1-to-10 differential clock distribution
•
Very low jitter (< 100 ps)
•
Operation from 2.2 V to 2.7 V AV
DD
and 2.3 V to 2.7 V V
DD
•
SSTL_2 interface clock inputs and outputs
•
HCSL to SSTL_2 input conversion
•
Test mode enables buffers while disabling PLL
•
Tolerant of Spread Spectrum input clock
•
3.3 V I
2
C support with 3.3 V V
DD
I
2
C
•
2.5 V I
2
C support with 2.5 V V
DD
I
2
C
•
Form, fit, and function compatible with CDCV850
DESCRIPTION
The PCK2057 is a high-performance, low-skew, low-jitter zero delay
buffer that distributes a differential clock input pair (CLK, CLK) to ten
differential pairs of clock outputs and one differential pair of
feedback clock outputs. The clock outputs are controlled by the
clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the
2-line serial interface (SDA, SCL), and the analog power input
(AV
DD
). The two-line serial interface (I
2
C) can put the individual
output clock pairs in a high-impedance state. When AV
DD
is tied to
GND, the PLL is turned off and bypassed for test purposes.
The device provides a standard mode (100 kbits) I
2
C interface for
device control. The implementation is as a slave/receiver. The serial
inputs (SDA, SCL) provide integrated pull-up resistors (typically
100 kΩ).
Two 8-bit, 2-line serial registers provide individual enable control for
each output pair. All outputs default to enabled at power-up. Each
output pair can be placed in a high-impedance mode, when a
low-level control bit is written to the control register. The registers
must be accessed in sequential order (i.e., random access of the
registers is not supported). The I
2
C interface circuit can be supplied
with either 2.5 V or 3.3 V (V
DD
I
2
C).
Since the PCK2057 is based on PLL circuitry, it requires a
stabilization time to achieve phase-lock of the PLL. This stabilization
time is required following power-up.
Y
4
22
Y
4
23
GND 24
SW00506
PIN DESCRIPTION
PINS
1, 7, 8, 18, 24, 25, 31,
41, 42, 48
2, 3, 5, 6, 9, 10, 19, 20,
22, 23, 26, 27, 29, 30,
32, 33, 39, 40, 43, 44,
46, 47
4, 11, 21, 28, 34, 38,
45
13, 14, 35, 36
SYMBOL
GND
DESCRIPTION
Ground
Buffered output
copies of input clock,
CLK
2.5 V supply
Differential clock
inputs and feedback
differential clock
inputs
Analog power
Analog ground
Serial data
Serial clock
I
2
C power
Y
n
, Y
n
,
FBOUT, FBOUT
V
DDQ
CLK, CLK,
FBIN, FBIN
16
17
37
12
15
AV
DD
AGND
SDA
SCL
V
DD
I
2
C
ORDERING INFORMATION
PACKAGES
48-Pin Plastic TSSOP
TEMPERATURE RANGE
0 to +70
°C
ORDER CODE
PCK2057DGG
DRAWING NUMBER
SOT362-1
2001 Jun 12
2
853–2253 26485
Philips Semiconductors
Product data
70 – 190 MHz I
2
C differential 1:10 clock driver
PCK2057
FUNCTION TABLE
INPUTS
AV
DD
GND
GND
2.5 V (nom.)
2.5 V (nom.)
CLK
L
H
L
H
CLK
H
L
H
L
Y
L
H
L
H
Y
H
L
H
L
OUTPUTS
1
FBOUT
L
H
L
H
FBOUT
H
L
H
L
Bypassed/OFF
Bypassed/OFF
ON
ON
PLL ON/OFF
NOTES:
H = HIGH voltage level
L = LOW voltage level
1. Each output pair (except FBOUT and FBOUT) can be put into a high-impedance state through the 2-line serial interface.
BLOCK DIAGRAM
SDA
CONTROL
LOGIC
SCL
Y
0
Y
0
Y
1
Y
1
Y
2
Y
2
Y
3
Y
3
Y
4
Y
4
PLL
FBIN
FBIN
AV
DD
Y
5
Y
5
Y
6
Y
6
Y
7
Y
7
Y
8
Y
8
Y
9
Y
9
FBOUT
FBOUT
CLK
CLK
SW00507
2001 Jun 12
3
Philips Semiconductors
Product data
70 – 190 MHz I
2
C differential 1:10 clock driver
PCK2057
I
2
C ADDRESS
1
1
0
1
0
0
1
R/W
su01394
I
2
C CONSIDERATIONS
I
2
C has been chosen as the serial bus interface to control the PCK2057. I
2
C was chosen to support the JEDEC proposal JC-42.5 168 Pin
Unbuffered SDRAM DIMM. All vendors are required to determine the legal issues associated with the manufacture of I
2
C devices.
1) Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if only
one master clock driver is used in a design. The address can be re-used for the CKBF device if no other conflicting I
2
C clock driver is used in
the system.
The following address was confirmed by Philips on 09/04/96.
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
0
2
C controller as a data direction bit. A ‘zero’ indicates a transmission (WRITE) to the clock device. A ‘one’
NOTE:
The R/W bit is used by the I
indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller to WRITE data; the
R/W bit of the address will always be seen as ‘zero’. Optimal address decoding of this bit is left to the vendor.
2) Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality required. Fast mode (400 kbits/s) functionality is optional.
3) Logic Levels: I
2
C logic levels are based on a percentage of V
DD
for the controller and other devices on the bus. Assume all devices are
based on a 3.3 Volt supply.
4) Data Byte Format: Byte format is 8 Bits as described in the following appendices.
5) Data Protocol: To simplify the clock I
2
C interface, the clock driver serial protocol was specified to use only block writes from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. Indexed bytes are not allowed. However, the SMBus controller has a more specific format than the generic I
2
C protocol.
The clock driver must meet this protocol which is more rigorous than previously stated I
2
C protocol. Treat the description from the viewpoint of
controller. The controller “writes” to the clock driver.
1 bit
Start bit
7 bits
Slave Address
1
R/W
1
Ack
8 bits
DUMMY
1
Ack
DUMMY
1 bit
Ack
8 bits
Data Byte 1
1
Ack
8 bits
Data Byte 2
1
Ack
1
Stop
SW00911
NOTE:
The acknowledgement bit is returned by the slave/receiver (the clock driver).
6) Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in section 15 of the I
2
C
specification.
a) Pull-Up Resistors: Any internal resistors pull-ups on the SDATA and SCLOCK inputs must be stated in the individual datasheet. The use of
internal pull-ups on these pins of below 100 kΩ is discouraged. Assume that the board designer will use a single external pull-up resistor for
each line and that these values are in the 5–6 kΩ range. Assume one I
2
C device per DIMM (serial presence detect), one I
2
C controller, one
clock driver plus one/two more I
2
C devices on the platform for capacitive loading purposes.
(b) Input Glitch Filters: Only fast mode I
2
C devices require input glitch filters to suppress bus noise. The clock driver is specified as a standard
mode device and is not required to support this feature.
For specific I
2
C information, consult the Philips I
2
C Peripherals Data Handbook IC12 (1997).
2001 Jun 12
4
Philips Semiconductors
Product data
70 – 190 MHz I
2
C differential 1:10 clock driver
PCK2057
SERIAL CONFIGURATION MAP
The serial bits will be read by the clock buffer in the following order:
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
All unused register bits (Reserved and “—”) should be designed as “Don’t Care”. It is expected that the controller will force all of these bits to a
“0” level.
All register bits labeled “Initialize to 0” must be written to zero during initialization. Failure to do so may result in a higher than normal operating
current.
Byte 0: Active/inactive register
1 = enable; 0 = disable
BIT
7
6
5
4
3
2
1
0
PIN#
2, 3
5, 6
9, 10
19, 20
22, 23
47, 46
44, 43
40, 39
NAME
CLK0, CLK0
CLK1, CLK1
CLK2, CLK2
CLK3, CLK3
CLK4, CLK4
CLK5, CLK5
CLK6, CLK6
CLK7, CLK7
INITIAL VALUE
1
1
1
1
1
1
1
1
DESCRIPTION
Enable/Disable Outputs
Enable/Disable Outputs
Enable/Disable Outputs
Enable/Disable Outputs
Enable/Disable Outputs
Enable/Disable Outputs
Enable/Disable Outputs
Enable/Disable Outputs
NOTE:
1. Inactive means outputs are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
Byte 1: Active/inactive register
1 = enable; 0 = disable
BIT
7
6
5
4
3
2
1
0
PIN#
30, 29
27, 26
—
—
—
—
—
—
NAME
CLK8, CLK8
CLK9, CLK9
—
—
—
—
—
—
INITIAL VALUE
1
1
0
0
0
0
0
0
DESCRIPTION
Enable/Disable Outputs
Enable/Disable Outputs
Reserved
Reserved
Reserved
Reserved
Power-Down Mode Disable/Enable
HCSL Enable/Disable
NOTE:
1. Inactive means outputs are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
京公网安备 11010802033920号
EEWORLD
