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821054PQFG

Description
Interface - CODECs QUAD PCM CODEC
CategoryWireless rf/communication    Telecom circuit   
File Size451KB,45 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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821054PQFG Overview

Interface - CODECs QUAD PCM CODEC

821054PQFG Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codePQFP
package instructionQFP-64
Contacts64
Manufacturer packaging codePMG64
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys Confidence3
Samacsys StatusReleased
Samacsys PartID851513
Samacsys Pin Count64
Samacsys Part CategoryIntegrated Circuit
Samacsys Package CategoryQuad Flat Packages
Samacsys Footprint NamePMG64
Samacsys Released Date2020-01-16 15:06:49
Is SamacsysN
Law of compression and extensionA/MU-LAW
filterYES
JESD-30 codeS-PQFP-G64
JESD-609 codee3
length14 mm
Humidity sensitivity level3
Number of functions1
Number of terminals64
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Package shapeSQUARE
Package formFLATPACK
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height2.45 mm
Nominal supply voltage5 V
surface mountYES
Telecom integrated circuit typesPCM CODEC
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
Base Number Matches1
QUAD PROGRAMMABLE PCM
CODEC WITH MPI INTERFACE
FEATURES
4-channel CODEC with on-chip digital filters
Software selectable A/
µ
-law, linear code conversion
Meets ITU-T G.711 - G.714 requirements
Programmable digital filters adapting to system demands:
- AC impedance matching
- Transhybrid balance
- Frequency response correction
- Gain setting
Supports two programmable PCM buses
Flexible PCM interface with up to 128 programmable time slots,
data rate from 512 kbits/s to 8.192 Mbits/s
MPI control interface
Broadcast mode for coefficient setting
7 SLIC signaling pins (including 2 debounced pins) per channel
Fast hardware ring trip mechanism
IDT821054
• 2 programmable tone generators per channel for testing,
ringing and DTMF generation
• 1 programmable FSK generator for sending Caller-ID messages
• Two programmable chopper clocks
• Master clock frequency selectable: 1.536 MHz, 1.544 MHz, 2.048
MHz, 3.072 MHz, 3.088 MHz, 4.096 MHz, 6.144 MHz, 6.176 MHz or
8.192 MHz
• Advanced test capabilities:
- 3 analog loopback tests
- 5 digital loopback tests
- Level metering function
• High analog driving capability (300
AC)
• TTL/CMOS compatible digital I/O
• CODEC identification
• +5 V single power supply
• Low power consumption
• Operating temperature range: -40°C to +85°C
• Package available: 64 Pin PQFP
FUNCTIONAL BLOCK DIAGRAM
CH1
VIN1
VOUT1
2 Inputs
3 I/Os
2 Outputs
Filter and A/D
D/A and Filter
CH3
Filter and A/D
D/A and Filter
VIN3
VOUT3
2 Inputs
3 I/Os
2 Outputs
DSP
Core
SLIC Signaling
SLIC Signaling
CH2
MCLK
CHCLK1
CHCLK2
CH4
DR1
DR2
DX1
DX2
PLL and Clock
Generation
General Control
Logic
MPI Interface
PCM Interface
RESET
INT12 INT34
CCLK
CS
CI
CO
FS BCLK
TSX1 TSX2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
2003
Integrated Device Technology, Inc.
FEBRUARY 26, 2003
DSC-6035/5

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