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843004AGI-04LF

Description
Clock Synthesizer / Jitter Cleaner 4 LVPECL OUT SYNTHESIZER
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size235KB,16 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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843004AGI-04LF Overview

Clock Synthesizer / Jitter Cleaner 4 LVPECL OUT SYNTHESIZER

843004AGI-04LF Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instruction4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
Contacts24
Manufacturer packaging codePGG24
Reach Compliance Codecompliant
ECCN codeEAR99
JESD-30 codeR-PDSO-G24
JESD-609 codee3
length7.8 mm
Humidity sensitivity level1
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Maximum output clock frequency680 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP24,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Master clock/crystal nominal frequency21.25 MHz
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum slew rate120 mA
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER
Base Number Matches1
FemtoClock
®
Crystal/LVCMOS-to-
3.3V LVPECL Frequency Synthesizer
G
ENERAL
D
ESCRIPTION
The 843004I-04 is a 4 output LVPECL Synthesizer optimized
to generate clock frequencies for a variety of high performance
applications. This device can select its input reference clock
from either a crystal input or a single-ended clock signal. It can
be configured to generate 4 outputs with individually selectable
divide-by-one or divide-by-four function via the 4 frequency
select pins (F_SEL[3:0]). The 843004I-04 uses IDT’s 3
rd
generation low phase noise VCO technology and can achieve
1ps or lower typical rms phase jitter. This ensures that it will
easily meet clocking requirements for SDH (STM-1/STM-4/STM-
16) and SONET (OC-3/OC12/OC-48). This device is suitable for
multi-rate and multiple port line card applications. The 843004I-
04 is conveniently packaged in a small 24-pin TSSOP package.
843004I-04
DATASHEET
F
EATURES
• Four LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following applications: SONET/SDH, SATA,
or 10Gb Ethernet
• Output frequency range: 140MHz - 170MHz,
560MHz - 680MHz
• VCO range: 560MHz - 680MHz
• Crystal oscillator and CLK range: 17.5MHz - 21.25MHz
• RMS phase jitter @ 622.08MHz output, using a 19.44MHz
crystal (12kHz - 20MHz): 0.82ps (typical)
• RMS phase jitter @ 156.25MHz output, using a 19.53125MHz
crystal (1.875MHz - 20MHz): 0.57ps (typical)
• RMS phase jitter @ 155.52MHz output, using a 19.44MHz
crystal (12kHz - 20MHz): 0.94ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free RoHS compliant package
B
LOCK
D
IAGRAM
XTAL_IN
P
IN
A
SSIGNMENT
÷1
Phase
Detector
VCO
÷4
0
1
Q0
nQ0
nQ1
Q1
V
CC
o
Q0
nQ0
MR
F_SEL3
nc
V
CCA
F_SEL0
V
CC
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
V
CCO
Q3
nQ3
V
EE
F_SEL2
INPUT_SEL
CLK
V
EE
XTAL_IN
XTAL_OUT
OSC
XTAL_OUT
CLK
Pulldown
INPUT_SEL
Pulldown
0
1
M = ÷32
MR
Pulldown
F_SEL0
Pullup
0
1
Q1
nQ1
F_SEL1
Pullup
843004I-04
0
1
Q2
nQ2
F_SEL2
Pullup
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
0
1
F_SEL3
Pullup
Q3
nQ3
843004I-04 REVISION A 5/27/15
1
©2015 Integrated Device Technology, Inc.

843004AGI-04LF Related Products

843004AGI-04LF
Description Clock Synthesizer / Jitter Cleaner 4 LVPECL OUT SYNTHESIZER
Brand Name Integrated Device Technology
Is it lead-free? Lead free
Is it Rohs certified? conform to
Maker IDT (Integrated Device Technology)
Parts packaging code TSSOP
package instruction 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
Contacts 24
Manufacturer packaging code PGG24
Reach Compliance Code compliant
ECCN code EAR99
JESD-30 code R-PDSO-G24
JESD-609 code e3
length 7.8 mm
Humidity sensitivity level 1
Number of terminals 24
Maximum operating temperature 85 °C
Minimum operating temperature -40 °C
Maximum output clock frequency 680 MHz
Package body material PLASTIC/EPOXY
encapsulated code TSSOP
Encapsulate equivalent code TSSOP24,.25
Package shape RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260
power supply 3.3 V
Master clock/crystal nominal frequency 21.25 MHz
Certification status Not Qualified
Maximum seat height 1.2 mm
Maximum slew rate 120 mA
Maximum supply voltage 3.465 V
Minimum supply voltage 3.135 V
Nominal supply voltage 3.3 V
surface mount YES
technology CMOS
Temperature level INDUSTRIAL
Terminal surface Matte Tin (Sn) - annealed
Terminal form GULL WING
Terminal pitch 0.65 mm
Terminal location DUAL
Maximum time at peak reflow temperature NOT SPECIFIED
width 4.4 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, OTHER
Base Number Matches 1
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