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MC74HC390ANG

Description
Counter Shift Registers 2-6V Dual 4-Stage Binary w/Divide-by-2
Categorylogic    logic   
File Size112KB,8 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Environmental Compliance
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MC74HC390ANG Overview

Counter Shift Registers 2-6V Dual 4-Stage Binary w/Divide-by-2

MC74HC390ANG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerON Semiconductor
Parts packaging codeDIP
package instructionHALOGEN AND ROHS COMPLIANT, PLASTIC, DIP-16
Contacts16
Reach Compliance Codeunknown
Factory Lead Time1 week
Other featuresONE FUNCTION HAS 1 BIT
Counting directionUP
seriesHC/UH
JESD-30 codeR-PDIP-T16
JESD-609 codee3
length19.175 mm
Load capacitance (CL)50 pF
Load/preset inputNO
Logic integrated circuit typeDECADE COUNTER
Maximum Frequency@Nom-Sup25000000 Hz
MaximumI(ol)0.004 A
Operating modeASYNCHRONOUS
Number of digits3
Number of functions2
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
method of packingRAIL
Peak Reflow Temperature (Celsius)260
power supply2/6 V
propagation delay (tpd)300 ns
Certification statusNot Qualified
Maximum seat height4.44 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
Trigger typeNEGATIVE EDGE
width7.62 mm
minfmax40 MHz
MC74HC390A
Dual 4-Stage Binary Ripple
Counter with
÷
2 and
÷
5
Sections
High−Performance Silicon−Gate CMOS
http://onsemi.com
The MC74HC390A is identical in pinout to the LS390. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4−bit counters, each
composed of a divide−by−two and a divide−by−five section. The
divide−by−two and divide−by−five counters have separate clock
inputs, and can be cascaded to implement various combinations of
÷
2
and/or
÷
5 up to a
÷
100 counter.
Flip−flops internal to the counters are triggered by high−to−low
transitions of the clock input. A separate, asynchronous reset is
provided for each 4−bit counter. State changes of the Q outputs do not
occur simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and should not
be used as clocks or strobes except when gated with the Clock of the
HC390A.
Features
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
CLOCK A
a
RESET a
Q
Aa
CLOCK B
a
Q
Ba
Q
Ca
Q
Da
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
CLOCK A
b
RESET b
Q
Ab
CLOCK B
b
Q
Bb
Q
Cb
Q
Db
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No 7 A
Chip Complexity: 244 FETs or 61 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MARKING DIAGRAMS
16
HC390AG
AWLYWW
1
SOIC−16
A
L, WL
Y, YY
W, WW
G or
G
1
TSSOP−16
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
16
HC
390A
ALYWG
G
(Note: Microdot may be in either location)
÷
2
COUNTER
3, 13
CLOCK A
1, 15
FUNCTION TABLE
Q
A
Clock
A
X
B
X
X
X
PIN 16 = V
CC
PIN 8 = GND
Reset
H
L
L
Action
Reset
÷
2 and
÷
5
Increment
÷
2
Increment
÷
5
5, 11
CLOCK B
4, 12
÷
5
COUNTER
Q
B
6, 10
Q
C
7, 9
Q
D
RESET
2, 14
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Figure 1. Logic Diagram
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 7
Publication Order Number:
MC74HC390A/D

MC74HC390ANG Related Products

MC74HC390ANG MC74HC390AFELG
Description Counter Shift Registers 2-6V Dual 4-Stage Binary w/Divide-by-2 Counter Shift Registers 2-6V Dual 4-Stage Binary w/Divide-by-2
Is it Rohs certified? conform to conform to
Maker ON Semiconductor ON Semiconductor
Parts packaging code DIP SOIC
package instruction HALOGEN AND ROHS COMPLIANT, PLASTIC, DIP-16 SOP, SOP16,.3
Contacts 16 16
Reach Compliance Code unknown unknown
Factory Lead Time 1 week 1 week
Other features ONE FUNCTION HAS 1 BIT ONE FUNCTION HAS 1 BIT
Counting direction UP UP
series HC/UH HC/UH
JESD-30 code R-PDIP-T16 R-PDSO-G16
JESD-609 code e3 e4
length 19.175 mm 10.2 mm
Load capacitance (CL) 50 pF 50 pF
Load/preset input NO NO
Logic integrated circuit type DECADE COUNTER DECADE COUNTER
Maximum Frequency@Nom-Sup 25000000 Hz 25000000 Hz
MaximumI(ol) 0.004 A 0.004 A
Operating mode ASYNCHRONOUS ASYNCHRONOUS
Number of digits 3 3
Number of functions 2 2
Number of terminals 16 16
Maximum operating temperature 125 °C 125 °C
Minimum operating temperature -55 °C -55 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP SOP
Encapsulate equivalent code DIP16,.3 SOP16,.3
Package shape RECTANGULAR RECTANGULAR
Package form IN-LINE SMALL OUTLINE
method of packing RAIL TAPE AND REEL
Peak Reflow Temperature (Celsius) 260 260
power supply 2/6 V 2/6 V
propagation delay (tpd) 300 ns 300 ns
Certification status Not Qualified Not Qualified
Maximum seat height 4.44 mm 2.05 mm
Maximum supply voltage (Vsup) 6 V 6 V
Minimum supply voltage (Vsup) 2 V 2 V
Nominal supply voltage (Vsup) 5 V 3 V
surface mount NO YES
technology CMOS CMOS
Temperature level MILITARY MILITARY
Terminal surface Matte Tin (Sn) - annealed Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form THROUGH-HOLE GULL WING
Terminal pitch 2.54 mm 1.27 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 40 40
Trigger type NEGATIVE EDGE NEGATIVE EDGE
width 7.62 mm 5.275 mm
minfmax 40 MHz 40 MHz
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