IDT72201L15JB datasheet, PDF - EEWORLD Datasheet

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IDT72201L15JB: Description512 X 9 OTHER FIFO, 15 ns, PQCC32; Categorystorage; File Size131KB，19 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT72201L15JB Overview

512 X 9 OTHER FIFO, 15 ns, PQCC32

IDT72201L15JB Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	32
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	5.5 V
Minimum supply/operating voltage	4.5 V
Rated supply voltage	5 V
maximum access time	15 ns
Processing package description	PLASTIC, LCC-32
state	ACTIVE
Craftsmanship	CMOS
packaging shape	RECTANGULAR
Package Size	CHIP CARRIER
surface mount	Yes
Terminal form	J BEND
Terminal spacing	1.27 mm
terminal coating	TIN LEAD
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	COMMERCIAL
memory width	9
organize	512 X 9
storage density	4608 deg
operating mode	SYNCHRONOUS
Number of digits	512 words
Number of digits	512
cycle	25 ns
Output enable	Yes
Memory IC type	OTHER FIFO

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IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

CMOS SyncFIFO™

64 X 9, 256 x 9, 512 x 9,

1024 X 9, 2048 X 9 and 4096 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Integrated Device Technology, Inc.

IDT72421

IDT72201

IDT72211

IDT72221

IDT72231

IDT72241

FEATURES:

•

64 x 9-bit organization (IDT72421)

256 x 9-bit organization (IDT72201)

512 x 9-bit organization (IDT72211)

1024 x 9-bit organization (IDT72221)

2048 x 9-bit organization (IDT72231)

4096 x 9-bit organization (IDT72241)

12 ns read/write cycle time (IDT72421/72201/72211)

15 ns read/write cycle time (IDT72221/72231/72241)

Read and write clocks can be independent

Dual-Ported zero fall-through time architecture

Empty and Full flags signal FIFO status

Programmable Almost-Empty and Almost-Full flags can

be set to any depth

Programmable Almost-Empty and Almost-Full flags

default to Empty+7, and Full-7, respectively

Output enable puts output data bus in high-impedance

state

Advanced submicron CMOS technology

Available in 32-pin plastic leaded chip carrier (PLCC),

ceramic leadless chip carrier (LCC), and 32-pin Thin

Quad Flat Pack (TQFP)

For Through-Hole product please see the IDT72420/

72200/72210/72220/72230/72240 data sheet

Military product compliant to MIL-STD-883, Class B

DESCRIPTION:

The IDT72421/72201/72211/72221/72231/72241

SyncFIFO™ are very high-speed, low-power First-In, First-

Out (FIFO) memories with clocked read and write controls.

The IDT72421/72201/72211/72221/72231/72241 have a 64,

256, 512, 1024, 2048, and 4096 x 9-bit memory array,

respectively. These FIFOs are applicable for a wide variety of

data buffering needs such as graphics, local area networks

and interprocessor communication.

These FIFOs have 9-bit input and output ports. The input

port is controlled by a free-running clock (WCLK), and two

write enable pins (

WEN1

, WEN2). Data is written into the

Synchronous FIFO on every rising clock edge when the write

enable pins are asserted. The output port is controlled by

another clock pin (RCLK) and two read enable pins (

REN1

REN2

). The read clock can be tied to the write clock for single

clock operation or the two clocks can run asynchronous of one

another for dual-clock operation. An output enable pin (

) is

provided on the read port for three-state control of the output.

The Synchronous FIFOs have two fixed flags, Empty (

)

and Full (

). Two programmable flags, Almost-Empty (

PAE

)

and Almost-Full (

PAF

), are provided for improved system

control. The programmable flags default to Empty+7 and Full-

7 for

PAE

and

PAF

, respectively. The programmable flag

offset loading is controlled by a simple state machine and is

initiated by asserting the load pin (

The IDT72421/72201/72211/72221/72231/72241 are

fabricated using IDT’s high-speed submicron CMOS

technology. Military grade product is manufactured in

compliance with the latest revision of MIL-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

WCLK

- D

WEN1

WEN2

INPUT REGISTER

OFFSET REGISTER

WRITE CONTROL

LOGIC

RAM ARRAY

64 x 9, 256 x 9,

512 x 9, 1024 x 9,

2048 x 9, 4096 x 9

FLAG

LOGIC

PAE

PAF

WRITE POINTER

READ POINTER

READ CONTROL

LOGIC

OUTPUT REGISTER

RESET LOGIC

RCLK

REN1

REN2

- Q

2655 drw 01

SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Integrated Device Technology, Inc

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

DECEMBER 1995

DSC-2655/6

5.07

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