CMOS PARALLEL-SERIAL FIFO
2048 x 9, 4096 x 9
Integrated Device Technology, Inc.
IDT72103
IDT72104
FEATURES:
• 35ns parallel port access time, 45ns cycle time
• 50MHz serial input/output frequency
• Serial-to-parallel, parallel-to-serial, serial-to-serial, and
parallel-to-parallel operations
• Expandable in both depth and width with no external
components
• Flexishift™ — Sets programmable serial word width
from 4 bits to any width with no external components
• Multiple flags: Full, Almost-Full (Full-1/8),Full-Minus-
One, Empty, Almost-Empty (Empty + 1/8), Empty-Plus
One, and Half-Full
• Asynchronous and simultaneous read or write
operations
• Dual-Port, zero fall-through time architecture
• Retransmit capability in single-device mode
• Packaged in 44-pin PLCC
• Industrial temperature range (-40
o
C to +85
o
C) is avail-
able, tested to military electrical specifications
APPLICATIONS:
•
•
•
•
•
•
•
•
•
High-speed data acquisition systems
Local area network (LAN) buffer
High-speed modem data buffer
Remote telemetry data buffer
FAX raster video data buffer
Laser printer engine data buffer
High-speed parallel bus-to-bus communications
Magnetic media controllers
Serial link buffer
DESCRIPTION:
The IDT72103/72104 are high-speed Parallel-Serial FlFOs
to be used with high-performance systems for functions such
as serial communications, laser printer engine control and
local area networks.
A serial input, a serial output and two 9-bit parallel ports
make four modes of data transfer possible: serial-to-parallel,
parallel-to-serial, serial-to-serial, and parallel-to-parallel. The
IDT72103/72104 are expandable in both depth and width for
all of these operational configurations.
FUNCTIONAL BLOCK DIAGRAM
SERIAL
INPUT
SI
SIX
SICP
DATA INPUTS (D
0
-D
8
)
SERIAL
INPUT
CIRCUITRY
FLAG
LOGIC
SERIAL/
PARALLEL
CONTROL
RAM ARRAY
2048 x 9
4096 x 9
SI
/PI
SO
/PO
W
XI
XO
FL
/
RT
FF
FF-1
EF+1
EF
AEF
HF
R
RS
WRITE
POINTER
READ
POINTER
DEPTH
EXPANSION
LOGIC
RESET
LOGIC
OE
DATA OUTPUTS (Q
0
-Q
8
)
The IDT logo is a registered trademark of Integrated Device Technology,Inc.
SERIAL
OUTPUT
CIRCUITRY
SERIAL
OUTPUT
SO
SOX
SOCP
2753 drw 01
COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-2753/8
5.37
1
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
COMMERCIAL TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
The IDT72103/72104 may be configured to handle serial
word widths of four or greater using IDT’s unique Flexishift
feature. Flexishift allows serial width and depth expansion
without external components. For example, you may config-
ure a 4K x 24 FIFO using three IDT72104s in a serial width
expansion configuration.
Seven flags are provided to signal memory status of the
FIFO. The flags are
FF
(Full),
AF
(7/8 full),
FF–1
(Full-minus-
one),
EF
(Empty),
AE
(1/8 full),
EF+1
(Empty-plus-one), and
HF
(Half-full).
Read (
R
) and Write (
W
) control pins are provided for
asynchronous and simultaneous operations. An output en-
able (
OE
) control pin is available on the parallel output port for
high-impedance control. The depth expansion control pins
XO
and
Xl
are provided to allow cascading for deeper FlFOs.
The IDT72103/72104 are manufactured using IDT’s CMOS
technology.
PIN CONFIGURATIONS
INDEX
D
0
XI
SO/PO
SOX
SOCP
SO
AEF
FF-1
FF
Q
0
GND
GND
D
1
D
2
D
3
D
4
W
V
CC
D
5
D
6
D
7
D
8
6
7
8
9
10
11
12
13
14
15
16
5
4
3
2
1
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
J44-1
17
29
18 19 20 21 22 23 24 25 26 27 28
GND
FL/RT
RS
SI
SICP
SIX
SI/PI
OE
EF+1
EF
XO/HF
Q
1
Q
2
Q
3
Q
4
GND
R
Q
5
Q
6
Q
7
Q
8
GND
PLCC
TOP VIEW
5.37
2753 drw 03
2
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
A
T
BIAS
T
STG
I
OUT
Rating
Terminal Voltage
with Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
DC Output Current
Commercial
–0.5 to +7.0
0 to +70
–55 to +125
–55 to +125
50
Unit
V
°C
°C
°C
mA
2753 tbl 01
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
12
Unit
pF
pF
2753 tbl 02
NOTE:
1. This parameter is sampled and not 100% tested.
RECOMMENDED DC OPERATING CONDITIONS
Symbol
V
CCC
GND
V
IH
V
IL(1)
Parameter
Commercial Supply
Voltage
Supply Voltage
Input High Voltage
Commercial
Input Low Voltage
Min.
4.5
0
2.0
—
Typ.
5.0
0
—
—
Max. Unit
5.5
0
—
0.8
V
V
V
V
2753 tbl 03
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
PIN DESCRIPTION
Symbol
D
0
-D
8
Name
Data Inputs
Serial Input Word
Width Select
Reset
Write
I/O
I/O
Description
In a parallel input configuration – data inputs for 9-bit wide data.
In a serial input configuration – one of the nine output pins is used to select the serial input
word width.
When
RS
is set low, internal READ and WRITE pointers are set to the first location of the RAM
array.
EF
,
EF+1
,
AEF
are all LOW after a reset, while
FF
,
FF-1
,
HF
are HIGH after a reset.
RS
W
I
I
A parallel word write cycle is initiated on the falling edge of
W
if the
FF
is high. When the FIFO
is full, FF will go low inhibiting further write operations to prevent data overflow. In a serial
input configuration, data bits are clocked into the input shift register and the write pointer does
not advance until a full parallel word is assembled. One of the pins, Di, is connected to
W
and
advances the write pointer every i-th serial input clock.
A read cycle is initiated on the falling edge of
R
if the
EF
is HIGH. After all the data from the
FIFO has been read
EF
will go LOW inhibiting further read operations. In a serial output
configuration, a data word is read from memory into the output shift register. One of the pins,
Qj, is connected to
R
and advances the read pointer every j-th serial output clock.
R
Read
I
FL
/
RT
Xl
OE
Q
0
-Q
8
First Load/
Retransmit
Expansion In
Output Enable
Data Outputs /
Serial Output
Word Width Select
Full Flag
Full-1 Flag
I
I
I
O
This is a dual-purpose pin. In multiple-device mode,
FL
/
RT
is grounded to indicate the first
device loaded. In single-device mode,
FL
/
RT
acts as the retransmit input. Single-device mode
is initiated by grounding the
XI
pin.
In single-device mode,
XI
is grounded.In depth expansion or daisy chain mode,
XI
is con
nected to the
XO
pin of the previous device.
When
OE
is LOW, both parallel and serial outputs are enabled. When
OE
is HIGH, the parallel
output buffers are placed in a high-impedance state.
In a parallel output configuration - data outputs for 9-bit wide data. In a serial output
configuration - one of nine output pins used to select the serial output word width.
FF
FF-1
O
O
FF
is asserted LOW when the FIFO is full and further write operations are inhibited. When
the
FF
is HIGH, the FIFO is not full and data can be written into the FIFO.
FF-1
goes LOW when the FIFO memory array is one word away from being full. It will remain
LOW when every memory location is filled.
2753 tbl 04
5.37
3
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION (Continued)
Symbol
Name
Expansion Out/
Half-Full Flag
I/O
O
Description
XO
/
HF
HF
is LOW when the FIFO is more than half-full in the single device or width expansion
modes. The
HF
will remain LOW until the difference between the write and read pointers is
less than or equal to one-half of the FIFO memory.
In depth expansion mode, a pulse is written from
XO
to
XI
of the next device when the last
location in the FIFO is filled. Another pulse is sent from
XO
to
Xl
of the next device when the
last FIFO location is read.
AEF
EF+1
EF
Sl
SO
SICP
SOCP
SIX
Almost-Empty/
Almost-Full Flag
Empty+1 Flag
Empty Flag
Serial Input
Serial Output
Serial Input Clock
Serial Output
Clock
Serial Input
Expansion
O
O
O
I
O
I
I
I
When
AEF
is LOW, the FIFO is empty to 1/8 full or 7/8 full to completely full. If
then the FIFO is greater than 1/8 full, but less than 7/8 full.
AEF
is HIGH,
EF+ 1
is LOW when there is zero or one word word in the FIFO memory array.
EF
goes LOW when the FIFO is empty and further read operations are inhibited.
FF
is HIGH
when the FIFO is not empty and data reads are permitted.
Data input for serial data.
Data output for serial data.
This pin is the serial input clock. On the rising edge of the SICP signal, new serial data bits
are read into the serial input shift register.
This pin is the serial output clock. On the rising edge of the SOCP signal, new serial data bits
are read from the serial output shift register.
SIX controls the serial input expansion for word widths greater than 9 bits. In a serial input
configuration, the SIX pin of the least significant device is tied HIGH. The SIX pin of all other
devices is connected to the D
8
pin of the previous device. In parallel input configurations or
serial input configurations of 9 bits or less, SIX is tied HIGH.
SOX controls the serial output expansion for word widths greater than 9 bits. In a serial output
configuration, the SOX pin of the least significant device is tied HIGH. The SOX pin of all other
devices is connected to the Q
8
pin of the previous device. In parallel output configurations
or serial output configurations of 9 bits or less, SOX is tied HIGH.
When this pin is HIGH, the FIFO is in a parallel input configuration and accepts input data
through D
0
-D
8
. When
SI
/PI is LOW, the FIFO is in a serial input configuration and data is input
through Sl.
When this pin is HIGH, the FIFO is in a parallel output configuration and sends output data
through Q
0
-Q
8
. When
SO
/PO is LOW the FIFO is in a serial output configuration and data
is input through SO.
One ground pin for the DIP package and five ground pins for the LCC/PLCC packages.
One + 5V power pin.
2753 tbl 05
SOX
Serial Output
Expansion
I
SI
/PI
SO
/PO
GND
V
CC
Serial/Parallel Input
I
Serial/Parallel Output
I
Ground
Power
5.37
4
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5.0V
±
10%, T
A
= 0°C to +70°C)
IDT72103/72104
Commercial
t
A
= 35, 50ns
Symbol
I
IL(1)
I
OL(2)
V
OH
V
OL
I
CC1(3)
I
CC2(3)
Parameter
Input Leakage Current
(Any Input)
Output Leakage Current
Output Logic "1" Voltage,
I
OUT
= -2mA
(4)
Output Logic "0" Voltage,
I
OUT
= 8mA
(5)
Average V
CC
Power Supply Current
Average Standby Current
(
R
=
W
=
RS
=
FL
/
RT
= V
IH
)
(SOCP = SICP = V
IL
)
Power Down Current
Min.
–1
–10
2.4
—
—
—
Typ.
—
—
—
—
90
8
Max.
1
10
—
0.4
140
12
Unit
µA
µA
V
V
mA
mA
I
CC3
(L)
(3,6)
—
—
2
mA
2753 tbl 06
NOTES:
1. Measurements with 0.4
≤
V
IN
≤
V
CC
.
2.
R
≥
V
IH
, SOCP
≤
VIL, 0.4
≤
V
OUT
≤
V
CC
.
3. I
CC
measurements are made with outputs open.
4. For SO, I
OUT
= -8mA.
5. For SO, I
OUT
=16mA.
6. SOCP = SICP
≤
0.2V; other Inputs = V
CC
-0.2V.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
2753 tbl 07
5V
1.1K
Ω
D.U.T.
680
Ω
30pF*
2753 drw 04
or equivalent circuit
Figure 1. Ouput Load
*Including jig and scope capacitances
5.37
5
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