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87339AGI-11LFT

Description
Clock Generators & Support Products Clock Generator
Categorylogic    logic   
File Size191KB,15 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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87339AGI-11LFT Overview

Clock Generators & Support Products Clock Generator

87339AGI-11LFT Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP20,.25
Contacts20
Manufacturer packaging codePGG20
Reach Compliance Codecompliant
ECCN codeEAR99
series87339
Input adjustmentDIFFERENTIAL
JESD-30 codeR-PDSO-G20
JESD-609 codee3
length6.5 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level1
Number of functions2
Number of inverted outputs
Number of terminals20
Actual output times4
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP20,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup2.1 ns
propagation delay (tpd)2.1 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.35 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
Base Number Matches1
Low Skew, ÷2/4,÷4/5/6,
Differential-to-3.3V LVPECL Clock Generator
87339I-11
Data Sheet
G
ENERAL
D
ESCRIPTION
T h e 8 7 3 3 9 I - 1 1 i s a l ow s kew, h i g h p e r fo r m a n c e
Differential-to-3.3V LVPECL Clock Generator/Divider. The
87339I-11 has one differential clock input pair. The CLK,
nCLK pair can accept most standard differential input
levels. The clock enable isinternally synchronized to
eliminate runt pulses on theoutputs during asynchronous as-
sertion/deassertion of the clock enable pin.
Guaranteed output and par t-to-par t skew charac-
teristics make the 87339I-11 ideal for clock distribution
applications demanding well defined performance and
repeatability.
F
EATURES
Dual ÷2, ÷4 differential 3.3V LVPECL outputs;
Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs
One differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum clock input frequency: 1GHz
Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
Output skew: 35ps (maximum)
Part-to-part skew: 385ps (maximum)
Bank skew: Bank A - 20ps (maximum)
Bank B - 20ps (maximum)
Propagation delay: 2.1ns (maximum)
LVPECL mode operating voltage supply range:
V
CC
= 3V to 3.6V, V
EE
= 0V
Available in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
87339I-11
20-Lead TSSOP
6.50mm x 4.40mm x 0.92 package body
G Package
Top View
20-Lead SOIC, 300MIL
7.5mm x 12.8mm x 2.25mm package body
M Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision B January 25, 2016
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