EPM7064AETC44-4 datasheet, PDF

Datasheet> All Categories > Programmable logic devices> Programmable logic> EPM7064AETC44-4

EPM7064AETC44-4: DescriptionCPLD - Complex Programmable Logic Devices CPLD - MAX 7000 64 Macro 36 IOs; CategoryProgrammable logic devices Programmable logic; File Size960KB，64 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

Download Datasheet Parametric View All

EPM7064AETC44-4 Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	EPM7064AETC44-4	-	-	View	Buy Now

EPM7064AETC44-4 Overview

CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 64 Macro 36 IOs

EPM7064AETC44-4 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	LQFP, TQFP44,.47SQ,32
Reach Compliance Code	compliant
ECCN code	EAR99
Architecture	PLA-TYPE
maximum clock frequency	222.2 MHz
In-system programmable	YES
JESD-30 code	S-PQFP-G44
JESD-609 code	e0
JTAG BST	YES
length	10 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	36
Number of entries	36
Number of macro cells	64
Output times	36
Number of product terms	2048
Number of terminals	44
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 36 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	TQFP44,.47SQ,32
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	235
power supply	2.5/3.3,3.3 V
Programmable logic type	EE PLD
propagation delay	4.5 ns
Certification status	Not Qualified
Maximum seat height	1.27 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	10 mm
Base Number Matches	1

Preview

Download Datasheet

View All

MAX 7000A

Includes

MAX 7000AE

Programmable Logic

Device

Data Sheet

September 2003, ver. 4.5

Features...

■

High-performance 3.3-V EEPROM-based programmable logic

devices (PLDs) built on second-generation Multiple Array MatriX

(MAX

) architecture (see

Table 1)

3.3-V in-system programmability (ISP) through the built-in

IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with

advanced pin-locking capability

–

MAX 7000AE device in-system programmability (ISP) circuitry

compliant with IEEE Std. 1532

–

EPM7128A and EPM7256A device ISP circuitry compatible with

IEEE Std. 1532

Built-in boundary-scan test (BST) circuitry compliant with

IEEE Std. 1149.1

Supports JEDEC Jam Standard Test and Programming Language

(STAPL) JESD-71

Enhanced ISP features

–

Enhanced ISP algorithm for faster programming (excluding

EPM7128A and EPM7256A devices)

–

ISP_Done bit to ensure complete programming (excluding

EPM7128A and EPM7256A devices)

–

Pull-up resistor on I/O pins during in-system programming

Pin-compatible with the popular 5.0-V MAX 7000S devices

High-density PLDs ranging from 600 to 10,000 usable gates

Extended temperature range

For information on in-system programmable 5.0-V MAX 7000 or 2.5-V

MAX 7000B devices, see the

MAX 7000 Programmable Logic Device Family

Data Sheet

or the

MAX 7000B Programmable Logic Device Family Data Sheet.

Altera Corporation

DS-M7000A-4.5

Recommended Resources

A brief discussion on the drawing skills of electrical control circuit diagrams

Converter circuit with 12V input and 9V, 7.5V or 6V output

Reverse-biased GaAsP light-emitting diode used as photosensor

FCOG6100 fully functional thyristor trigger circuit

Digital AC Wattmeter Circuit

Transistor driven DC motor

I would like to ask everyone, why can't my SD card always generate the target code?: SDHC:由两个文件夹组成；SDHC 和 SDHCBase SDHC文件内容：!if 0 Copyright (c) Microsoft Corporation.All rights reserved. !endif !if 0 Use of this source code is subject to the terms of the Microsoft end-user license agr...; wangtou Embedded System

Why would the filter added to the final stage cavity be burned?: This is a high-power PW device in the L bandAs shown in the pictureThe design requirements of the filter are also high powerThe picture belowScrewThere are traces of burns in the picture...; btty038 RF/Wirelessly

AD10 chip shielded power inductor packaging: I would like to ask where I can find the 12*12*7 chip power inductor package 127 series in the component library, or can I only draw it myself? Also, if the conventional package of the chip aluminum e...; bule PCB Design

Yuan Fang, what do you think of this circuit? (7-End): [align=center][font=punctuation, 微软雅黑, Tohoma][size=12px][color=rgb(0, 0, 0)][font=微软雅黑][color=#000000][size=26px]Yuan Fang, what do you think of this circuit? (7-End)[/size][/color][/font][/color][/s...; okhxyyo Analogue and Mixed Signal

Tips to reduce the damage to hard disk caused by BT downloads: Tips to reduce the damage to hard disk caused by BT downloadsAlthough BT download is very popular now, and there are many resources on the Internet, it seems that more and more people think that BT do...; fighting Embedded System

【Signal Processing】Digital Signal Processing FPGA Implementation Utilities and Files: Good things found Share it...; 常见泽1 FPGA/CPLD

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components