IDT71V2579YS75PF datasheet, PDF

Datasheet> All Categories > IDT71V2579YS75PF

Preview

IDT71V2579YS75PF: Description128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect; File Size293KB，22 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

Download Datasheet View All

IDT71V2579YS75PF Overview

128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect

Preview

Download Datasheet

View All

128K x 36, 256K x 18

3.3V Synchronous SRAMs

2.5V I/O, Flow-Through Outputs

Burst Counter, Single Cycle Deselect

Features

IDT71V2577S

IDT71V2579S

IDT71V2577SA

IDT71V2579SA

Description

The IDT71V2577/79 are high-speed SRAMs organized as

128K x 36/256K x 18. The IDT71V2577/79 SRAMs contain write, data,

address and control registers. There are no registers in the data output

path (flow-through architecture). Internal logic allows the SRAM to

generate a self-timed write based upon a decision which can be left until

the end of the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V2577/79 can provide four cycles of data

for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will flow-through from the

array after a clock-to-data access time delay from the rising clock edge of

the same cycle. If burst mode operation is selected (ADV=LOW), the

subsequent three cycles of output data will be available to the user on the

next three rising clock edges. The order of these three addresses are

defined by the internal burst counter and the

LBO

input pin.

The IDT71V2577/79 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and a 165 fine pitch ball grid array (fBGA).

Input

Output

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

N/A

4877 tbl 01

128K x 36, 256K x 18 memory configurations

Supports fast access times:

Commercial:

– 7.5ns up to 117MHz clock frequency

Commercial and Industrial:

– 8.0ns up to 100MHz clock frequency

– 8.5ns up to 87MHz clock frequency

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte write

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array (fBGA)

Pin Description Summary

-A

BWE

(1)

CLK

ADV

ADSC

ADSP

LBO

TMS

TDI

TCK

TDO

TRST

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Output

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

NOTE:

and

are not applicable for the IDT71V2579.

JUNE 2003

DSC-4877/08

Recommended Resources

2△-Y-△ connection three-speed motor contactor control circuit

Transistor common emitter circuit

CD4541 cadmium nickel battery automatic charging circuit diagram

Gantry milling machine trigger schematic circuit

Optical pulse generator circuit

Frequency characteristics of ultrasonic sensors

Four physical models of IoT systems: The three-layer conceptual model of the Internet of Things has a wide influence. It is very helpful for understanding the difference between the Internet of Things and the Internet. However, when it c...; Jacktang Robotics Development

How to operate LM3S I/O like 51, a very small trick: I just came back from a business trip to Shenyang. I finally saw the board I had been eyeing for for a long time. I was so excited. HahahaI have been learning TI 's ARM for a while, but I always feel ...; dyc1229 Microcontroller MCU

JK trigger problem help: I would like to ask everyone, in the circuit, the J/K input terminal is connected to the 5V voltage terminal, and the clk input terminal is connected to the front-end TTL signal, so what is the final ...; 小可姐 Analog electronics

Memory basics: Memory basics...; simonprince Analog electronics

ARM simple OS question: Now I want to use ARM to write a simple OS. I need to create a process table, then read the content of the process from the process table, run it, delete the process, and then read the next one. The c...; linfmaing08 ARM Technology

How to convert integer type into floating point type in VHDL language?: Please give me some advice, thank you....; my_style FPGA/CPLD

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components