IDT71V25761S200PFI datasheet, PDF

Datasheet> All Categories > IDT71V25761S200PFI

Preview

IDT71V25761S200PFI: Description128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect; File Size516KB，23 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

Download Datasheet View All

IDT71V25761S200PFI Overview

128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preview

Download Datasheet

View All

128K X 36, 256K X 18

3.3V Synchronous SRAMs

2.5V I/O, Pipelined Outputs,

Burst Counter, Single Cycle Deselect

IDT71V25761

IDT71V25781

Features

128K x 36, 256K x 18 memory configurations

Supports high system speed:

Commercial:

– 200MHz 3.1ns clock access time

Commercial and Industrial:

– 183MHz 3.3ns clock access time

– 166MHz 3.5ns clock access time

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte write

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array

Description

The IDT71V25761/781 are high-speed SRAMs organized as 128K

x 36/256K x 18. The IDT71V25761/781 SRAMs contain write, data,

address and control registers. Internal logic allows the SRAM to generate

a self-timed write based upon a decision which can be left until the end of

the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V25761/718 can provide four cycles of data

for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will be pipelined for one

cycle before it is available on the next rising clock edge. If burst mode

operation is selected (ADV=LOW), the subsequent three cycles of output

data will be available to the user on the next three rising clock edges. The

order of these three addresses are defined by the internal burst counter

and the

LBO

input pin.

The IDT71V25761/781 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and 165 fine pitch ball grid array (fBGA).

Pin Description Summary

-A

BWE

(1)

CLK

ADV

ADSC

ADSP

LBO

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

N/A

5297 tbl 01

NOTE:

and

are not applicable for the IDT71V25781.

OCTOBER 2000

DSC-5297/01

Recommended Resources

Internal structure of overvoltage converter

JK7 proximity switch circuit

OTL tube amplifier circuit

Electrical schematic diagram of B220 gantry planer (2)

Music linear voltage controlled oscillator circuit diagram

555 single/dual trace oscilloscope conversion circuit

We are planning to start two new projects after the new year and are looking for relevant talents. . .: [font=微软雅黑][size=4]I'll release this information first. If you are interested, please contact me first (just send a private message on the site) [/size][/font] [font=微软雅黑][size=4]The projects will be ...; cardin6 Creative Market

Indoor Positioning: For example, I put A at the other end of the wall, and then B (movable) can automatically detect the direction and distance of A anywhere in the room, and move to point A (the device can only be AB, a...; 562327931 RF/Wirelessly

【R7F0C809】Development board: I received the R7F0C809. I have been busy recently and have not reported it. Here is the board and report. Without further ado, here are the pictures. I received the express delivery. It is a very big...; chris_shang Renesas Electronics MCUs

Happy engineers, so happy industry journalists!: [size=5][color=#ff0000]Event details>>[url=https://www.eeworld.com.cn/USB_Type-C/]Happy engineers, so happy industry journalists! [/url][/color][/size] [color=#ff0000]Event time: [/color][color=#3e3a3...; EEWORLD社区 Analogue and Mixed Signal

What will the elevators of the future look like?: According to the United Nations Department of Economic and Social Affairs, by 2050, two-thirds of the world's population will live in cities. With the rapid advancement of urbanization, people can use...; qwqwqw2088 Analogue and Mixed Signal

Please recommend a solution for boosting 2V to 8V. The larger and more stable the output current, the better! !: The voltage of the solar cell power input fluctuates greatly between 0.8V and 3.5V, and the current stability is also very poor. I would like to ask you to recommend a solution to boost the output to ...; TheSun Power technology

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components