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IDT71V256SA12YGI8

Description
32K X 8 CACHE SRAM, 12 ns, PDSO28
Categorystorage   
File Size471KB,8 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric View All

IDT71V256SA12YGI8 Overview

32K X 8 CACHE SRAM, 12 ns, PDSO28

IDT71V256SA12YGI8 Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals28
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage3.6 V
Minimum supply/operating voltage3 V
Rated supply voltage3.3 V
maximum access time12 ns
Processing package description0.300 INCH, ROHS COMPLIANT, SOJ-28
Lead-freeYes
EU RoHS regulationsYes
stateACTIVE
CraftsmanshipCMOS
packaging shapeRectangle
Package SizeSMALL OUTLINE
surface mountYes
Terminal formJ BEND
Terminal spacing1.27 mm
terminal coatingMATTE Tin
Terminal locationpair
Packaging MaterialsPlastic/Epoxy
Temperature levelINDUSTRIAL
memory width8
organize32K × 8
storage density262144 deg
operating modeASYNCHRONOUS
Number of digits32768 words
Number of digits32K
Memory IC typecache static random access memory
serial parallelparallel
Lower Power
3.3V CMOS Fast SRAM
256K (32K x 8-Bit)
Features
Ideal for high-performance processor secondary cache
Commercial (0°C to +70°C) and Industrial (–40°C to +85°C)
temperature range options
Fast access times:
– Commercial and Industrial: 10/12/15/20ns
Low standby current (maximum):
– 2mA full standby
Small packages for space-efficient layouts:
– 28-pin 300 mil SOJ
– 28-pin TSOP Type I
Produced with advanced high-performance CMOS
technology
Inputs and outputs are LVTTL-compatible
Single 3.3V(±0.3V) power supply
IDT71V256SA
Description
The IDT71V256SA is a 262,144-bit high-speed static RAM organized
as 32K x 8. It is fabricated using IDT’s high-performance, high-reliability
CMOS technology.
The IDT71V256SA has outstanding low power characteristics while
at the same time maintaining very high performance. Address access
times of as fast as 10ns are ideal for 3.3V secondary cache in 3.3V
desktop designs.
When power management logic puts the IDT71V256SA in standby
mode, its very low power characteristics contribute to extended battery life.
By taking
CS
HIGH, the SRAM will automatically go to a low power standby
mode and will remain in standby as long as
CS
remains HIGH. Further-
more, under full standby mode (CS at CMOS level, f=0), power consump-
tion is guaranteed to always be less than 6.6mW and typically will be much
smaller.
The IDT71V256SA is packaged in a 28-pin 300 mil SOJ and a 28-pin
300 mil TSOP Type I.
Functional Block Diagram
A
0
ADDRESS
DECODER
A
14
262,144 BIT
MEMORY ARRAY
V
CC
GND
I/O
0
INPUT
DATA
CIRCUIT
I/O
7
I/O CONTROL
CS
OE
WE
,
CONTROL
CIRCUIT
3101 drw 01
JANUARY 2004
1
©2004 Integrated Device Technology, Inc.
DSC-3101/08
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