IDT7140SA25L48G datasheet, PDF

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IDT7140SA25L48G: Description1K X 8 DUAL-PORT SRAM, 100 ns, PQFP64; Categorystorage; File Size156KB，19 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT7140SA25L48G Overview

1K X 8 DUAL-PORT SRAM, 100 ns, PQFP64

IDT7140SA25L48G Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	64
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	5.5 V
Minimum supply/operating voltage	4.5 V
Rated supply voltage	5 V
maximum access time	100 ns
Processing package description	14 × 14 MM, 1.40 MM HEIGHT, Green, TQFP-64
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK, low PROFILE
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.8000 mm
terminal coating	MATTE Tin
Terminal location	Four
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
memory width	8
organize	1K × 8
storage density	8192 deg
operating mode	ASYNCHRONOUS
Number of digits	1024 words
Number of digits	1K
Memory IC type	dual-port static random access memory
serial parallel	parallel

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HIGH SPEED

1K X 8 DUAL-PORT

STATIC SRAM

Features

High-speed access

– Commercial: 20/25/35/55/100ns (max.)

– Industrial: 25/55/100ns (max.)

– Military: 25/35/55/100ns (max.)

Low-power operation

– IDT7130/IDT7140SA

—

Active: 550mW (typ.)

—

Standby: 5mW (typ.)

– IDT7130/IDT7140LA

—

Active: 550mW (typ.)

—

Standby: 1mW (typ.)

MASTER IDT7130 easily expands data bus width to 16-or-

more-bits using SLAVE IDT7140

IDT7130SA/LA

IDT7140SA/LA

◆

On-chip port arbitration logic (IDT7130 Only)

BUSY

output flag on IDT7130;

BUSY

input on IDT7140

INT

flag for port-to-port communication

Fully asynchronous operation from either port

Battery backup operation–2V data retention (LA only)

TTL-compatible, single 5V ±10% power supply

Military product compliant to MIL-PRF-38535 QML

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin

PLCC, and 64-pin STQFP and TQFP

Green parts available, see ordering information

Functional Block Diagram

R/W

I/O

- I/O

I/O

Control

BUSY

(1,2)

I/O

-I/O

I/O

Control

BUSY

Address

Decoder

(1,2)

MEMORY

ARRAY

Address

Decoder

R/W

ARBITRATION

and

INTERRUPT

LOGIC

R/W

INT

(2)

INT

2689 drw 01

(2)

NOTES:

1. IDT7130 (MASTER):

BUSY

is open drain output and requires pullup resistor.

IDT7140 (SLAVE):

BUSY

is input.

2. Open drain output: requires pullup resistor.

APRIL 2006

DSC-2689/13

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