IC42S16100
512K x 16 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11 (bank select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto refresh, self refresh
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable
CAS
latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Byte controlled by LDQM and UDQM
• Package 400mil 50-pin TSOP-2
• Pb(lead)-free package is available
DESCRIPTION
ICSI
's 16Mb Synchronous DRAM IC42S16100 is organized
as a 524,288-word x 16-bit x 2-bank for improved
performance. The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS
50-Pin TSOP-2
VCC
I/O0
I/O1
GNDQ
I/O2
I/O3
VCCQ
I/O4
I/O5
GNDQ
I/O6
I/O7
VCCQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
GND
I/O15
I/O14
GNDQ
I/O13
I/O12
VCCQ
I/O11
I/O10
GNDQ
I/O9
I/O8
VCCQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A11
A0-A10
A11
A0-A7
I/O0 to I/O15
CLK
CKE
CS
RAS
Address Input
Row Address Input
Bank Select Address
Column Address Input
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
CAS
WE
LDQM
UDQM
Vcc
GND
VccQ
GNDQ
NC
Column Address Strobe Command
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
IC42S16100
PIN FUNCTIONS
Pin No.
20 to 24
27 to 32
Symbol
A0-A10
Type
Input Pin
Function (In Detail)
A0 to A10 are address inputs. A0-A10 are used as row address inputs during active
command input and A0-A7 as column address inputs during read or write command
input. A10 is also used to determine the precharge mode during other commands. If
A10 is LOW during precharge command, the bank selected by A11 is precharged,
but if A10 is HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts automati-
cally after the burst access.
These signals become part of the OP CODE during mode register set command
input.
A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when
high, bank 1 is selected. This signal becomes part of the OP CODE during mode
register set command input.
CAS,
in conjunction with the
RAS
and
WE,
forms the device command. See the
"Command Truth Table" item for details on device commands.
The CKE input determines whether the CLK input is enabled within the device.
When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when
LOW, invalid. When CKE is LOW, the device will be in either the power-down mode,
the clock suspend mode, or the self refresh mode. The CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this
device are acquired in synchronization with the rising edge of this pin.
The
CS
input determines whether command input is enabled within the device.
Command input is enabled when
CS
is LOW, and disabled with
CS
is HIGH. The
device remains in the previous state when
CS
is HIGH.
I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units
using the LDQM and UDQM pins.
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go
to the HIGH impedance state when LDQM/UDQM is HIGH. This function corre-
sponds to
OE
in conventional DRAMs. In write mode, LDQM and UDQM control the
input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is
enabled, and data can be written to the device. When LDQM or UDQM is HIGH,
input data is masked and cannot be written to the device.
RAS,
in conjunction with
CAS
and
WE,
forms the device command. See the
"Command Truth Table" item for details on device commands.
WE,
in conjunction with
RAS
and
CAS,
forms the device command. See the
"Command Truth Table" item for details on device commands.
V
CC
Q is the output buffer power supply.
V
CC
is the device internal power supply.
GNDQ is the output buffer ground.
GND is the device internal ground.
19
A11
Input Pin
16
34
CAS
CKE
Input Pin
Input Pin
35
18
CLK
CS
Input Pin
Input Pin
2, 3, 5, 6, 8, 9, 11 I/O0 to
12, 39, 40, 42, 43, I/O15
45, 46, 48, 49
14, 36
LDQM,
UDQM
I/O Pin
Input Pin
17
15
7, 13, 38, 44
1, 25
4, 10, 41, 47
26, 50
RAS
WE
V
CC
Q
V
CC
GNDQ
GND
Input Pin
Input Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
3
IC42S16100
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
CC MAX
V
CCQ MAX
V
IN
V
OUT
P
D MAX
I
CS
T
OPR
T
STG
Parameters
Maximum Supply Voltage
Maximum Supply Voltage for Output Buffer
Input Voltage
Output Voltage
Allowable Power Dissipation
Output Shorted Current
Operating Temperature
Storage Temperature
Rating
–1.0 to +4.6
–1.0 to +4.6
–1.0 to +4.6
–1.0 to +4.6
1
50
0 to +70
–55 to +150
Unit
V
V
V
V
W
mA
°C
°C
DC RECOMMENDED OPERATING CONDITIONS
(2)
(
At T
A
= 0 to +70°C)
Symbol
V
CC
, V
CC
Q
V
IH
V
IL
Parameter
Supply Voltage
Input High Voltage
(3)
Input Low Voltage
(4)
Min.
3.0
2.0
-0.3
Typ.
3.3
—
—
Max.
3.6
V
DD
+ 0.3
+0.8
Unit
V
V
V
CAPACITANCE CHARACTERISTICS
(1,2)
(At T
A
= 0 to +25°C, Vcc = VccQ = 3.3 ± 0.3V, f = 1 MHz)
Symbol
C
IN
1
C
IN
2
CI/O
Parameter
Input Capacitance: A0-A11
Input Capacitance: (CLK, CKE,
CS, RAS, CAS, WE,
LDQM, UDQM)
Data Input/Output Capacitance: I/O0-I/O15
Typ.
—
—
—
Max.
4
4
5
Unit
pF
pF
pF
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All voltages are referenced to GND.
3. V
IH
(max) = V
CCQ
+ 2.0V with a pulse width
≤
3 ns.
4. V
IL
(min) = GND – 2.0V with a pulse < 3 ns and -1.5V with a pulse < 5ns.
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
5
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