HY62SF16406D Series
256Kx16bit full CMOS SRAM
Document Title
256K x16 bit 1.7 ~ 2.3V Super Low Power FCMOS Slow SRAM
Revision History
Revision No
00
01
02
03
History
Initial Draft
Changed Logo
Changed Isb1 values
Changed Package Size (6.1mm -> 6.0mm)
Draft Date
Dec.20.2000
Mar.23.2001
Jun.07.2001
Aug.07.2001
Remark
Preliminary
Preliminary
Preliminary
Preliminary
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev.03 / Aug.01
Hynix Semiconductor
HY62SF16406D Series
Preliminary
DESCRIPTION
The HY62SF16406D is a high speed, super low
power and 4Mbit full CMOS SRAM organized as
256K words by 16bits. The HY62SF16406D uses
high performance full CMOS process technology
and is designed for high speed and low power
circuit technology. It is particularly well-suited for
the high density low power system application.
This device has a data retention mode that
guarantees data to remain valid at a minimum
power supply voltage of 1.2V.
FEATURES
•
Fully static operation and Tri-state output
•
TTL compatible inputs and outputs
•
Battery backup
-. 1.2V(min) data retention
•
Standard pin configuration
-. 48-ball FBGA
Product No.
Voltage
(V)
Speed (ns)
70/85
Operation
Current/Icc(mA)
3
HY62SF16406D-I 1.7~2.3
Note 1. I : Industrial
2. Current value is max.
Standby
Current(uA)
LL
SL
12
6
Temperature
(°C)
-40~85
PIN CONNECTION
1
2
/OE
/UB
3
A0
A3
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
/CS1
IO2
IO4
IO5
IO6
6
CS2
IO1
ADD INPUT
BUFFER
BLOCK DIAGRAM
ROW
DECODER
SENSE AMP
A
B
C
D
E
F
G
H
/LB
IO9
I/O1
COLUMN
DECODER
IO10 IO11 A5
Vss
Vcc
IO12 A17
IO13 NC
IO3
Vcc
Vss
IO7
A17
I/O8
DATA I/O
BUFFER
PRE DECODER
MEMORY ARRAY
256K x 16
WRITE DRIVER
I/O9
BLOCK
DECODER
IO15 IO14 A14
IO16 NC
NC
A8
A12
A9
I/O16
/WE IO8
A11
NC
FBGA
/CS1
CS2
/OE
/LB
/UB
/WE
PIN DESCRIPTION
Pin Name
/CS1, CS2
/WE
/OE
/LB
/UB
Pin Function
Chip Select
Write Enable
Output Enable
Lower Byte Control (I/O1~I/O8)
Upper Byte Control (I/O9~I/O16)
Pin Name
I/O1~I/O16
A0~A17
Vcc
Vss
NC
Pin Function
Data Inputs/Outputs
Address Inputs
Power (1.7~2.3V)
Ground
No Connection
Rev.03 / Aug.01
2
HY62SF16406D Series
ORDERING INFORMATION
Part No.
HY62SF16406D-DF(I)
HY62SF16406D-SF(I)
Speed
70/85
70/85
Power
LL-part
SL-part
Temp
.
I
I
Package
FBGA
FBGA
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
V
IN,
V
OUT
Vcc
T
A
T
STG
P
D
T
SOLDER
Parameter
Input/Output Voltage
Power Supply
Operating Temperature
Storage Temperature
Power Dissipation
Ball Soldering Temperature & Time
Rating
-0.3 to 2.6
-0.3 to 3.6
-40 to 85
-55 to 150
1.0
260
•
10
Unit
V
V
°C
°C
W
°C•sec
Remark
HY62SF16406D-I
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS1
H
X
X
L
L
CS2
X
L
X
H
H
/WE
X
X
X
H
H
/OE
X
X
X
H
L
/LB
X
X
H
L
X
L
H
L
L
H
L
/UB
X
X
H
X
L
H
L
L
H
L
L
Mode
Deselected
Output Disabled
Read
I/O Pin
I/O1~I/O8
I/O9~I/O16
Hi-Z
Hi-Z
D
OUT
Hi-Z
D
OUT
D
IN
Hi-Z
D
IN
Hi-Z
Hi-Z
Hi-Z
D
OUT
D
OUT
Hi-Z
D
IN
D
IN
Power
Standby
Active
Active
L
H
L
X
Write
Active
Note:
1. H=V
IH
, L=V
IL
, X=don't care (V
IL or
V
IH
)
2. /UB, /LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When /LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8.
When /UB is LOW, data is written or read to the upper byte, I/O 9 -I/O 16.
Rev.03 / Aug.01
2
HY62SF16406D Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Vss
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
1.7
0
1.4
-0.3
1.
Typ
1.8
0
-
-
Max.
2.3
0
Vcc+0.3
0.4
Unit
V
V
V
V
Note : 1. Undershoot : VIL = -1.5V for pulse width less than 30ns
2. Undershoot is sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS
T
A
= -40°C to 85°C
Sym
Parameter
I
LI
Input Leakage Current
I
LO
Output Leakage Current
Test Condition
Vss < V
IN
< Vcc
Vss < V
OUT
< Vcc,
/CS1 = V
IH
or CS2=V
IL
or
/
OE
=
V
IH
or /WE = V
IL
or
/
UB
=
V
IH ,
/LB = V
IH
/CS1 = V
IL
, CS2=V
IH
,
V
IN
= V
IH
or V
IL,
I
I/O =
0mA
/CS1 = V
IL,
CS2 = V
IH
,
V
IN
= V
IH
or V
IL,
Cycle Time = Min,
100% Duty, I
I/O =
0mA
/CS1 < 0.2V
,
CS2 > Vcc-0.2V,
V
IN
< 0.2V or V
IN
> Vcc-0.2V
,
Cycle Time = 1us,
100% Duty, I
I/O =
0mA
/CS1 = V
IH
or CS2 = V
IL
or
/UB, /LB = V
IH
V
IN
= V
IH
or V
IL
/CS1 > Vcc - 0.2V or
SL
CS2 < Vss + 0.2V or
/UB, /LB > Vcc - 0.2V
V
IN
> Vcc - 0.2V or
LL
V
IN
< Vss + 0.2V
I
OL
= 0.1mA
I
OH =
-0.1mA
Min
-1
-1
Typ
1.
-
-
Max
1
1
Unit
uA
uA
Icc
Operating Power Supply Current
3
20
mA
mA
I
CC1
Average Operating Current
3
mA
I
SB
Standby Current
(TTL Input)
0.3
0.2
6
mA
uA
I
SB1
Standby Current
(CMOS Input)
0.2
-
1.6
-
-
12
0.2
-
uA
V
V
V
OL
V
OH
Output Low
Output High
Note
1. Typical values are at Vcc = 1.8V T
A
= 25°C
2. Typical values are not 100% tested
CAPACITANCE
(Temp = 25°C, f= 1.0MHz)
Symbol
Parameter
C
IN
Input Capacitance (Add, /CS1,CS2,/LB,/UB, /WE, /OE)
C
OUT
Output Capacitance (I/O)
Note : These parameters are sampled and not 100% tested
Condition
V
IN
= 0V
V
I/O
= 0V
Max.
8
10
Unit
pF
pF
Rev.03 / Aug.01
3
HY62SF16406D Series
AC CHARACTERISTICS
T
A
= -40°C to 85°C, unless otherwise specified
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Symbol
Parameter
70ns
Min.
Max.
70
-
-
-
-
10
5
10
0
0
0
10
70
60
60
60
0
50
0
0
30
0
5
-
70
70
35
70
-
-
-
30
30
30
-
-
-
-
-
-
-
-
20
-
-
-
85ns
Min.
Max.
85
-
-
-
-
10
5
10
0
0
0
10
85
70
70
70
0
60
0
0
35
0
5
-
85
85
40
85
-
-
-
30
30
30
-
-
-
-
-
-
-
-
25
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address Access Time
tACS
Chip Select Access Time
tOE
Output Enable to Output Valid
tBA
/LB, /UB Access Time
tCLZ
Chip Select to Output in Low Z
tOLZ
Output Enable to Output in Low Z
tBLZ
/LB, /UB Enable to Output in Low Z
tCHZ
Chip Deselection to Output in High Z
tOHZ
Out Disable to Output in High Z
tBHZ
/LB, /UB Disable to Output in High Z
tOH
Output Hold from Address Change
WRITE CYCLE
tWC
Write Cycle Time
tCW
Chip Selection to End of Write
tAW
Address Valid to End of Write
tBW
/LB, /UB Valid to End of Write
tAS
Address Set-up Time
tWP
Write Pulse Width
tWR
Write Recovery Time
tWHZ
Write to Output in High Z
tDW
Data to Write Time Overlap
tDH
Data Hold from Write Time
tOW
Output Active from End of Write
AC TEST CONDITIONS
T
A
= -40°C to 85°C, unless otherwise specified
Parameter
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Level
Output Load tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW
Others
Value
0.4V to 1.6V
5ns
0.9V
CL = 5pF + 1TTL Load
CL = 30pF + 1TTL Load
AC TEST LOADS
V
TM
=1.8V
4091 Ohm
D
OUT
CL(1)
3273 Ohm
Note 1. Including jig and scope capacitance:
Rev.03 / Aug.01
4
京公网安备 11010802033920号
EEWORLD
