HY57V561620BLT-HI datasheet, PDF

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HY57V561620BLT-HI: Description4 Banks x 4M x 16Bit Synchronous DRAM; Categorystorage storage; File Size156KB，12 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY57V561620BLT-HI Overview

4 Banks x 4M x 16Bit Synchronous DRAM

HY57V561620BLT-HI Parametric

Parameter Name	Attribute value
Maker	SK Hynix
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP54,.46,32
Contacts	54
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G54
JESD-609 code	e6
length	22.238 mm
memory density	268435456 bi
Memory IC Type	SYNCHRONOUS DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	54
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	16MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP54,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.194 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.001 A
Maximum slew rate	0.22 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN BISMUTH
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
width	10.16 mm

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HY57V561620B(L)T-I

4 Banks x 4M x 16Bit Synchronous DRAM

DESCRIPTION

The HY57V561620B-I is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require

large memory density and high bandwidth. HY57V561620B is organized as 4banks of 4,194,304x16.

HY57V561620B-I is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by

a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or

write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or

write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

All device pins are compatible with LVTTL interface

JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin

pitch

All inputs and outputs referenced to positive edge of sys-

tem clock

Data mask function by UDQM, LDQM

Internal four banks operation

•

Auto refresh and self refresh

8192 refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

•

- 1, 2, 4 or 8 for Interleave Burst

Programmable CAS Latency ; 2, 3 Clocks

Ambient Temperature : - 40 ~ 85

°C

•

ORDERING INFORMATION

Part No.

HY57V561620BT-6I

HY57V561620BT-KI

HY57V561620BT-HI

HY57V561620BT-8I

HY57V561620BT-PI

HY57V561620BT-SI

HY57V561620BLT-6I

HY57V561620BLT-KI

HY57V561620BLT-HI

HY57V561620BLT-8I

HY57V561620BLT-PI

HY57V561620BLT-SI

Clock Frequency

166MHz

133MHz

125MHz

100MHz

166MHz

133MHz

125MHz

100MHz

Power

Organization

Interface

Package

Normal

4Banks x 4Mbits x16

LVTTL

400mil 54pin TSOP II

Low power

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev.1.3 / Apr. 2003

HY57V561620BLT-HI Related Products

	HY57V561620BLT-HI	HY57V561620B	HY57V561620BT-I	HY57V561620LT-I
Description	4 Banks x 4M x 16Bit Synchronous DRAM	4 Banks x 4M x 16Bit Synchronous DRAM	4 Banks x 4M x 16Bit Synchronous DRAM	4 Banks x 4M x 16Bit Synchronous DRAM

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