DS1867
Dual Digital Potentiometer with EEPROM
www.dalsemi.com
FEATURES
§
Nonvolatile version of the popular DS1267
§
Low power consumption, quiet, pumpless
design
§
Operates from single 5V or
±5V
supplies
§
Two digitally controlled, 256-position
potentiometers
§
Wiper position is maintained in the absence of
power
§
Serial port provides means for setting and
reading both potentiometers
§
Resistors can be connected in series to
provide increased total resistance
§
16-pin SOIC and 20-pin TSSOP for surface
mount applications
§
Standard resistance values:
- DS1867-10 ~ 10 kΩ
- DS1867-50 ~ 50 kΩ
- DS1867-100 ~ 100 kΩ
§
Operating Temperature Range:
- Industrial: -40° to +85°
C
C
PIN ASSIGNMENT
V
B
H1
L1
W1
RST
CLK
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
S
OUT
WO
HO
LO
C
OUT
DQ
14-Pin DIP (300-mil)
See Mech. Drawings Section
V
B
NC
H1
L1
W1
RST
CLK
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
NC
S
OUT
WO
HO
LO
C
OUT
DQ
PIN DESCRIPTION
L0, L1
H0, H1
W1, W2
V
B
S
OUT
RST
16-Pin SOIC (300-mil)
DQ
CLK
C
OUT
V
CC
GND
NC
DNC
-
-
-
-
-
-
-
-
-
-
-
-
-
Low End of Resistor
High End of Resistor
Wiper End of Resistor
Substrate Bias
Wiper for Stacked Configuration
Serial Port Reset Input
Serial Port Data Input
Serial Port Clock Input
Cascade Serial Port Output
+5-Volt Supply Input
Ground
No Internal Connection
Do Not Connect
See Mech. Drawings Section
V
B
NC
H1
L1
W1
RST
CLK
DNC
DNC
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
DNC
DNC
S
OUT
WO
HO
LO
C
OUT
DNC
DQ
20-Pin TSSOP (173-mil)
See Mech. Drawings Section
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DS1867
DESCRIPTION
The DS1867 Dual Digital Potentiometer with EEPROM is the nonvolatile version of the popular DS1267
Dual Digital Potentiometer. The DS1867 consists of two digitally controlled potentiometers having 256-
position wiper settings. Wiper position is maintained in the absence of power through the use of
EEPROM memory cell arrays. Communication and control of the device are accomplished over a 3-wire
serial port which allows reads and writes of the wiper position. Both potentiometers can be stacked for
increased total resistance with the same resolution. For multiple-device, single-processor environments,
the DS1867 can be cascaded for control over a single 3-wire bus. The DS1867 is offered in three standard
resistance values.
OPERATION
The DS1867 contains two 256-position potentiometers whose wiper positions are set by an 8-bit value.
These two 8-bit values are written to a 17-bit I/O shift register which is used to store wiper position and
the stack select bit when the device is powered. An additional memory area, the shadow memory, stores
the 17-bit I/O shift register during a power-down sequence which provides for wiper nonvolatility. A
block diagram of the DS1867 is presented in Figure 1.
Communication and control of the DS1867 is accomplished through a 3-wire serial port interface that
drives an internal control logic unit. The 3-wire serial interface consists of the three input signals:
RST
,
CLK, and DQ.
The
RST
control signal is used to enable 3-wire serial port operation of the device. The
RST
signal is an
active high input and is required to begin any communication to the DS1867. The CLK signal input is
used to provide timing synchronization for data input and output. The DQ signal line is used to transmit
potentiometer wiper settings and the stack select bit configuration to the 17-bit I/O shift register of the
DS1867.
Figure 2(a) presents the 3-wire serial port protocol. As shown, the 3-wire port is inactive when the
RST
signal input is low. Communication with the DS1867 requires the transition of the
RST
input from a low
state to a high state. Once the 3-wire port has been activated, data is latched into the part on the low to
high transition of the CLK signal input. Three-wire serial timing requirements are provided in the timing
diagrams of Figure 2(b) and (c).
Data written to the DS1867 over the 3-wire serial interface is stored in the 17-bit I/O shift register (see
Figure 3). The 17-bit I/O shift register contains both 8-bit potentiometer wiper position values and the
stack select bit. The composition of the I/O shift register is presented in Figure 3. Bit 0 of the I/O shift
register contains the stack select bit. This bit will be discussed in the section entitled Stacked
Configuration. Bits 1 through 8 of the I/O shift register contain the potentiometer-1 wiper position value.
Bit 1 will contain the MSB of the wiper setting for potentiometer-1 and bit 8 the LSB for the wiper
setting. Bits 9 through 16 of the I/O shift register contain the value of the potentiometer-0 wiper position
with the MSB for the wiper position occupying bit 9 and the LSB bit 16.
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DS1867 BLOCK DIAGRAM
Figure 1
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DS1867
TIMING DIAGFRAMS
Figure 2
(
a) 3-Wire Serial Interface General Overview
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DS1867
I/O SHIFT REGISTER
Figure 3
17-BIT I/O SHIFT REGISTER
Transmission of data always begins with the stack select bit followed by the potentiometer-1 wiper
position value and lastly the potentiometer-0 wiper position value (see Figure 2(a)).
When wiper position data is to be written to the DS1867, 17-bits (or some integer multiple) of data should
always be transmitted. Transactions which do not send a complete 17-bits (or multiple) will leave the
register incomplete and possibly an error in desired wiper position. After a communication transaction
has been completed the
RST
signal input should be taken to a low state to prevent any inadvertent
changes to the device shift register. Once
RST
has reached a low state, the contents of the I/O shift
register are loaded into the respective multiplexers for setting wiper position. A new wiper position will
only engage pending a
RST
transition to the low state. The wiper position for the high-end terminals H0
and H1 will have data values FF (hex), while the low-end terminals will have data values 00 (hex).
STACKED CONFIGURATION
The potentiometers of the DS1867 can be connected in series as shown in Figure 4. This is referred to as
the stacked configuration and allows the user to double the total end-to-end resistance of the part. The
resolution of the combined potentiometers will remain the same as a single potentiometer but with a total
of 512 wiper positions available. Device resolution is defined as R
TOT
/256 (per potentiometer); where
R
TOT
is equal to the device resistance value. The wiper output for the combined stacked potentiometer will
be taken at the S
out
pin, which is the multiplexed output of the wiper of potentiometer-0 (W0) or
potentiometer-1 (W1). The potentiometer wiper selected at the S
out
output is governed by the setting of
the stack select bit (bit-0) of the 17-bit I/O shift register. If the stack select bit has value 0, the multiplexed
output, S
out
, will be that of the potentiometer-0 wiper. If the stack select bit has value 1, the multiplexed
output, S
out
, will be that of the potentiometer-1 wiper.
STACKED CONFIGURATION
Figure 4
CASCADE OPERATION
A feature of the DS1867 is the ability to control multiple devices from a single processor. Multiple
DS1867s can be linked or daisy-chained as shown in Figure 5. As a data bit is entered into the I/O shift
register of the DS1867 it will appear at the C
out
output after a maximum delay of 70 nanoseconds.
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