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HM1-65642C/883

Description
8K X 8 STANDARD SRAM, 200 ns, CDIP28
Categorystorage   
File Size191KB,11 Pages
ManufacturerIntersil ( Renesas )
Websitehttp://www.intersil.com/cda/home/
Download Datasheet Parametric Compare View All

HM1-65642C/883 Overview

8K X 8 STANDARD SRAM, 200 ns, CDIP28

HM1-65642C/883 Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals28
Maximum operating temperature125 Cel
Minimum operating temperature-55 Cel
Maximum supply/operating voltage5.5 V
Minimum supply/operating voltage4.5 V
Rated supply voltage5 V
maximum access time200 ns
Processing package descriptionCERAMIC, DIP-28
stateDISCONTINUED
CraftsmanshipCMOS
packaging shapeRECTANGULAR
Package SizeIN-LINE
Terminal formTHROUGH-HOLE
Terminal spacing2.54 mm
Terminal locationDUAL
Packaging MaterialsCERAMIC, GLASS-SEALED
Temperature levelMILITARY
memory width8
organize8K X 8
storage density65536 deg
operating modeASYNCHRONOUS
Number of digits8192 words
Number of digits8K
Memory IC typeSTANDARD SRAM
serial parallelPARALLEL
®
HM-65642/883
8K x 8 Asynchronous
CMOS Static RAM
Description
The HM-65642/883 is a CMOS 8192 x 8-bit Static Random
Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide
standard, which allows easy memory board layouts which
accommodate a variety of industry standard ROM, PROM,
EPROM, EEPROM and RAMs. The HM-65642/883 is ideally
suited for use in microprocessor based systems. In particu-
lar, interfacing with the Intersil 80C86 and 80C88 micropro-
cessors is simplified by the convenient output enable (G)
input.
The HM-65642/883 is a full CMOS RAM which utilizes an
array of six transistor (6T) memory cells for the most stable
and lowest possible standby supply current over the full mili-
tary temperature range.
May 2002
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Full CMOS Design
• Six Transistor Memory Cell
• Low Standby Supply Current . . . . . . . . . . . . . . . . 100µA
• Low Operating Supply Current. . . . . . . . . . . . . . . 20mA
• Fast Address Access Time . . . . . . . . . . . . . . . . . . 150ns
• Low Data Retention Supply Voltage . . . . . . . . . . . 2.0V
• CMOS/TTL Compatible Inputs/Outputs
• JEDEC Approved Pinout
• Equal Cycle and Access Times
• No Clocks or Strobes Required
• Gated Inputs
- No Pull-Up or Pull-Down Resistors Required
• Temperature Range -55
o
C to +125
o
C
• Easy Microprocessor Interfacing
• Dual Chip Enable Control
Ordering Information
PACKAGE
CERDIP
CLCC
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
150ns/75µA
HM1-65642B/883
HM4-65642B/883
150ns/150µA
HM1-65642/883
HM4-65642/883
200ns/250µA
HM1-65642C/883
-
PKG. NO.
F28.6
J32.A
Pinouts
HM-65642/883 (CERDIP)
TOP VIEW
NC 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
DQ0 11
DQ1 12
DQ2 13
GND 14
28 VCC
27 W
26 E2
25 A8
24 A9
23 A11
22 G
21 A10
20 E1
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
A6
A5
A4
A3
A2
5
6
7
8
9
HM4-65642/883 (CLCC)
TOP VIEW
VCC
A12
NC
NC
A7
E2
W
4
3
2
1
32
31
30
29 A8
28 A9
27 A11
26 NC
25 G
24 A10
23 E1
22 DQ7
21 DQ6
PIN
A
DQ
E1
E2
W
G
NC
GND
VCC
DESCRIPTION
Address Input
Data Input/Output
Chip Enable
Chip Enable
Write Enable
Output Enable
No Connections
Ground
Power
A1 10
A0
NC
DQ0
11
12
13
14
DQ1
15 16
DQ2
GND
17
NC
18
DQ3
19
DQ4
20
DQ5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN3004.2
220

HM1-65642C/883 Related Products

HM1-65642C/883 HM-65642/883 HM-65642_02 HM1-65642/883 HM1-65642B/883 HM4-65642B/883 HM4-65642/883
Description 8K X 8 STANDARD SRAM, 200 ns, CDIP28 8K X 8 STANDARD SRAM, 150 ns, CDIP28 8K X 8 STANDARD SRAM, 150 ns, CDIP28 8K X 8 STANDARD SRAM, 150 ns, CDIP28 8K X 8 STANDARD SRAM, 150 ns, CDIP28 8K X 8 STANDARD SRAM, 150 ns, CQCC32 8K X 8 STANDARD SRAM, 150 ns, CQCC32
Number of functions 1 1 1 1 1 - -
Number of terminals 28 28 28 28 28 - -
Maximum operating temperature 125 Cel 125 Cel 125 Cel 125 Cel 125 Cel - -
Minimum operating temperature -55 Cel -55 Cel -55 Cel -55 Cel -55 Cel - -
Maximum supply/operating voltage 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V - -
Minimum supply/operating voltage 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V - -
Rated supply voltage 5 V 5 V 5 V 5 V 5 V - -
maximum access time 200 ns 150 ns 150 ns 150 ns 150 ns - -
Processing package description CERAMIC, DIP-28 CERAMIC, DIP-28 CERAMIC, DIP-28 CERAMIC, DIP-28 CERAMIC, DIP-28 - -
state DISCONTINUED ACTIVE ACTIVE ACTIVE ACTIVE - -
Craftsmanship CMOS CMOS CMOS CMOS CMOS - -
packaging shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR - -
Package Size IN-LINE IN-LINE IN-LINE IN-LINE IN-LINE - -
Terminal form THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE - -
Terminal spacing 2.54 mm 2.54 mm 2.54 mm 2.54 mm 2.54 mm - -
Terminal location DUAL DUAL DUAL DUAL DUAL - -
Packaging Materials CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED - -
Temperature level MILITARY MILITARY MILITARY MILITARY MILITARY - -
memory width 8 8 8 8 8 - -
organize 8K X 8 8K X 8 8K X 8 8K X 8 8K X 8 - -
storage density 65536 deg 65536 deg 65536 deg 65536 deg 65536 deg - -
operating mode ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS - -
Number of digits 8K 8K 8K 8K 8K - -
Memory IC type STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM - -
serial parallel PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL - -
terminal coating - TIN LEAD TIN LEAD TIN LEAD TIN LEAD - -
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