a
FEATURES
Fast Throughput Rate: 3 MSPS
Wide Input Bandwidth: 40 MHz
No Pipeline Delays with SAR ADC
Excellent DC Accuracy Performance
Two Parallel Interface Modes
Low Power:
90 mW (Full Power) and 2.5 mW (NAP Mode)
Standby Mode: 2 A Max
Single 5 V Supply Operation
Internal 2.5 V Reference
Full-Scale Overrange Mode (using 13th Bit)
System Offset Removal via User Access Offset Register
Nominal 0 V to 2.5 V Input with Shifted Range
Capability
14-Bit Pin Compatible Upgrade AD7484 Available
3 MSPS, 12-Bit SAR ADC
AD7482
FUNCTIONAL BLOCK DIAGRAM
AV
DD
AGND
C
BIAS
DV
DD
V
DRIVE
DGND
REFOUT
2.5 V
REFERENCE
REFSEL
BUF
REFIN
VIN
T/H
12-BIT
ALGORITHMIC SAR
AD7482
MODE1
MODE2
CLIP
NAP
STBY
RESET
CONVST
D12
D11
D10
D9
D8
D7
D6
D5
CONTROL
LOGIC AND I/O
REGISTERS
GENERAL DESCRIPTION
The AD7482 is a 12-bit, high speed, low power, successive-
approximation ADC. The part features a parallel interface with
throughput rates up to 3 MSPS. The part contains a low noise,
wide bandwidth track-and-hold that can handle input fre-
quencies in excess of 40 MHz.
The conversion process is a proprietary algorithmic successive-
approximation technique that results in no pipeline delays. The
input signal is sampled, and a conversion is initiated on the
falling edge of the
CONVST
signal. The conversion process is
controlled via an internally trimmed oscillator. Interfacing is via
standard parallel signal lines, making the part directly compat-
ible with microcontrollers and DSPs.
The AD7482 provides excellent ac and dc performance specifi-
cations. Factory trimming ensures high dc accuracy resulting in
very low INL, offset, and gain errors.
The part uses advanced design techniques to achieve very low
power dissipation at high throughput rates. Power consumption
in the normal mode of operation is 90 mW. There are two power-
saving modes: a NAP Mode that keeps the reference circuitry alive
for a quick power-up while consuming 2.5 mW, and a STANDBY
Mode that reduces power consumption to a mere 10
µW.
The AD7482 features an on-board 2.5 V reference but can also
accommodate an externally provided 2.5 V reference source. The
nominal analog input range is 0 V to 2.5 V, but an offset shift
capability allows this nominal range to be offset by
±
200 mV.
This allows the user considerable flexibility in setting the bottom
end reference point of the signal range, a useful feature when
using single-supply op amps.
The AD7482 also provides the user with an 8% overrange
capability via a 13th bit. Thus, if the analog input range strays
outside the nominal by up to 8%, the user can still accurately
resolve the signal by using the 13th bit.
The AD7482 is powered by a 4.75 V to 5.25 V supply. The part
also provides a V
DRIVE
Pin that allows the user to set the voltage
levels for the digital interface lines. The range for this V
DRIVE
Pin
is 2.7 V to 5.25 V. The part is housed in a 48-lead LQFP package
and is specified over a –40°C to +85°C temperature range.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
CS
RD
WRITE
BUSY
D0
D1
D2
D3
D4
AD7482–SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
2, 3
Signal-to-Noise + Distortion (SINAD)
4
Total Harmonic Distortion (THD)
4
4
1
(V
DD
= 5 V
±
5%, AGND = DGND = 0 V, V
REF
= External, f
SAMPLE
= 3 MSPS; all specifi-
cations T
MIN
to T
MAX
and valid for V
DRIVE
= 2.7 V to 5.25 V, unless otherwise noted.)
Unit
dB min
dB typ
dB typ
dB max
dB typ
dB typ
dB max
dB typ
dB typ
ns typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB typ
LSB max
LSB typ
LSB max
%FSR max
LSB max
%FSR max
mV min
V max
µA
max
µA
typ
pF typ
V
µA
max
pF typ
µA
typ
V typ
mV typ
mV max
Ω
typ
V min
V max
µA
max
pF max
Test Conditions/Comments
F
IN
= 1 MHz
F
IN
= 1 MHz
F
IN
= 1 MHz, Internal Reference
Internal Reference
Specification
71
72
71
–86
–90
–88
–87
–96
–94
10
40
3.5
12
±
0.5
±
1
±
0.25
±
0.5
±
0.25
±
1.5
0.036
±
1.5
0.036
–200
+2.7
±
1
±
2
35
+2.5
±
1
25
220
+2.5
±
50
±
100
1
V
DRIVE
–1
0.4
±
1
10
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
4
Second Order Terms
Third Order Terms
Aperture Delay
Full-Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
4
Differential Nonlinearity
4
Offset Error
4
Gain Error
4
ANALOG INPUT
Input Voltage
DC Leakage Current
Input Capacitance
5
REFERENCE INPUT/OUTPUT
V
REFIN
Input Voltage
V
REFIN
Input DC Leakage Current
V
REFIN
Input Capacitance
5
V
REFIN
Input Current
V
REFOUT
Output Voltage
V
REFOUT
Error @ 25°C
V
REFOUT
Error T
MIN
to T
MAX
V
REFOUT
Output Impedance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN5
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
5
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time(t
ACQ
)
Throughput Rate
F
IN1
= 95.053 kHz, F
IN2
= 105.329 kHz
@ 3 dB
@ 0.1 dB
B Grade
A Grade
Guaranteed No Missed Codes to 12 Bits
V
IN
from 0 V to 2.7 V
V
IN
= –200 mV
±
1% for Specified Performance
External Reference
0.7
×
V
DRIVE
V min
0.3
×
V
DRIVE
V max
±
10
µA
max
10
pF max
Straight (Natural) Binary
300
70
70
2.5
3
–2–
ns max
ns max
ns max
MSPS max
MSPS max
Sine Wave Input
Full-Scale Step Input
Parallel Mode 1
Parallel Mode 2
REV. 0
AD7482
SPECIFICATIONS
(continued)
Parameter
POWER REQUIREMENTS
V
DD
V
DRIVE
I
DD
Normal Mode (Static)
Normal Mode (Operational)
NAP Mode
Standby Mode
Power Dissipation
Normal Mode (Operational)
NAP Mode
Standby Mode
6
(V
DD
= 5 V
±
5%, AGND = DGND = 0 V, V
REF
= External, f
SAMPLE
= 3 MSPS; all specifications T
MIN
to T
MAX
and valid for V
DRIVE
= 2.7 V to 5.25 V, unless otherwise noted.)
Specification
5
2.7
5.25
12
18
0.5
2
0.5
90
2.5
10
Unit
V
V min
V max
mA max
mA max
mA max
µA
max
µA
typ
mW max
mW max
µW
max
Test Conditions/Comments
±
5%
CS
and
RD
= Logic 1
NOTES
1
Temperature range is as follows: –40°C to +85°C.
2
SNR and SINAD figures quoted include external analog input circuit noise contribution of approximately 1 dB.
3
See Typical Performance Characteristics section for analog input circuits used.
4
See Terminology section.
5
Sample tested @ 25°C to ensure compliance.
6
Digital input levels at GND or V
DRIVE
.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
Parameter
*
(V
DD
= 5 V
±
5%, AGND = DGND = 0 V, V
REF
= External; all specifications T
MIN
to T
MAX
and valid for
V
DRIVE
= 2.7 V to 5.25 V, unless otherwise noted.)
Symbol
t
CONV
t
QUIET
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
14
t
15
t
9
t
10
t
11
t
12
t
13
Min
Typ
Max
300
100
5
20
0
25
30
5
10
0
30
30
5
2
6
5
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA READ
Conversion Time
Quiet Time before Conversion Start
CONVST
Pulsewidth
CONVST
Falling Edge to
BUSY
Falling Edge
CS
Falling Edge to
RD
Falling Edge
Data Access Time
CONVST
Falling Edge to New Data Valid
BUSY
Rising Edge to New Data Valid
Bus Relinquish Time
RD
Rising Edge to
CS
Rising Edge
CS
Pulsewidth
RD
Pulsewidth
DATA WRITE
WRITE Pulsewidth
Data Setup Time
Data Hold Time
CS
Falling Edge to WRITE Falling Edge
WRITE Falling Edge to
CS
Rising Edge
Specifications subject to change without notice.
*All
timing specifications given above are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used.
REV. 0
–3–
AD7482
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C, unless otherwise noted.)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DRIVE
to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND . . . . . –0.3 V to AV
DD
+ 0.3 V
Digital Input Voltage to GND . . . . . –0.3 V to V
DRIVE
+ 0.3 V
REFIN to GND . . . . . . . . . . . . . . . . –0.3 V to AV
DD
+ 0.3 V
Input Current to Any Pin except Supplies . . . . . . . . .
±
10 mA
Operating Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 50°C/W
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 10°C/W
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
JA
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
PIN CONFIGURATION
CONVST
D12
MODE1
MODE2
RESET
AGND
AGND
AV
DD
CLIP
D11
D10
48 47 46 45 44 43 42 41 40 39 38 37
AV
DD 1
C
BIAS 2
AGND
3
AGND
4
AV
DD 5
AGND
6
VIN
7
REFOUT
8
REFIN
9
REFSEL
10
AGND
11
AGND
12
D9
36
D8
35
D7
34
D6
33
D5
32
V
DRIVE
31
DGND
30
DGND
29
DV
DD
28
D4
27
D3
26
D2
25
D1
PIN 1
IDENTIFIER
AD7482
TOP VIEW
(Not to Scale)
13 14 15 16 17 18 19 20 21 22 23 24
AGND
AGND
NAP
RD
WRITE
BUSY
R1
R2
AV
DD
ORDERING GUIDE
Model
AD7482AST
AD7482BST
EVAL-AD7482CB
1
EVAL-CONTROL BRD2
2
Temperature Range
–40°C to +85°C
–40°C to +85°C
Evaluation Board
Controller Board
STBY
CS
Integral Nonlinearity (INL)
±
1 LSB Max
±
0.5 LSB Max
D0
Package Options
ST-48 (LQFP)
ST-48 (LQFP)
NOTES
1
This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.
2
This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7482 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD7482
PIN FUNCTION DESCRIPTIONS
Pin
Number
1, 5, 13, 46
2
3, 4, 6, 11, 12,
14, 15, 47, 48
7
8
9
10
Mnemonic
AV
DD
C
BIAS
AGND
VIN
REFOUT
REFIN
REFSEL
Description
Positive Power Supply for Analog Circuitry
Decoupling Pin for Internal Bias Voltage. A 1 nF capacitor should be placed between this pin
and AGND.
Power Supply Ground for Analog Circuitry
Analog Input. Single-ended analog input channel.
Reference Output. REFOUT connects to the output of the internal 2.5 V reference buffer. A 470 nF
capacitor must be placed between this pin and AGND.
Reference Input. A 470 nF capacitor must be placed between this pin and AGND. When using an
external voltage reference source, the reference voltage should be applied to this pin.
Reference Decoupling Pin. When using the internal reference, a 1 nF capacitor must be connected
from this pin to AGND. When using an external reference source, this pin should be connected
directly to AGND.
Standby Logic Input. When this pin is logic high, the device will be placed in Standby Mode.
See Power Saving section for further details.
NAP Logic Input. When this pin is logic high, the device will be placed in a very low power mode.
See Power Saving section for further details.
Chip Select Logic Input. This pin is used in conjunction with
RD
to access the conversion result.
The databus is brought out of three-state and the current contents of the output register driven
onto the data lines following the falling edge of both
CS
and
RD. CS
is also used in conjunction
with WRITE to perform a write to the offset register.
CS
can be hardwired permanently low.
Read Logic Input. Used in conjunction with
CS
to access the conversion result.
Write Logic Input. Used in conjunction with
CS
to write data to the offset register. When the
desired offset word has been placed on the databus, the WRITE line should be pulsed high. It is
the falling edge of this pulse that latches the word into the offset register.
Busy Logic Output. This pin indicates the status of the conversion process. The
BUSY
signal goes
low after the falling edge of
CONVST
and stays low for the duration of the conversion. In Parallel
Mode 1, the
BUSY
signal returns high when the conversion result has been latched into the output
register. In Parallel Mode 2, the
BUSY
signal returns high as soon as the conversion has been
completed, but the conversion result does not get latched into the output register until the falling
edge of the next
CONVST
pulse.
These pins should be pulled to ground via 100 kΩ resistors.
Data I/O Bits (D11 is MSB). These are three-state pins that are controlled by
CS, RD,
and
WRITE. The operating voltage level for these pins is determined by the V
DRIVE
input.
Positive Power Supply for Digital Circuitry
Ground Reference for Digital Circuitry
Logic Power Supply Input. The voltage supplied at this pin will determine at what voltage the
interface logic of the device will operate.
Data Output Bit for Overranging. If the overrange feature is not used, this pin should be pulled to
DGND via a 100 kΩ resistor.
Convert Start Logic Input. A conversion is initiated on the falling edge of the
CONVST
signal.
The input track-and-hold amplifier goes from track mode to hold mode and the conversion process
commences.
Reset Logic Input. A falling edge on this pin resets the internal state machine and terminates a
conversion that may be in progress. The contents of the offset register will also be cleared on this
edge. Holding this pin low keeps the part in a reset state.
Operating Mode Logic Input. See Table III for details.
Operating Mode Logic Input. See Table III for details.
Logic Input. A logic high on this pin enables output clipping. In this mode, any input voltage that
is greater than positive full scale or less than negative full scale will be clipped to all “1s” or all “0s,”
respectively. Further details are given in the Offset/Overrange section.
16
17
18
STBY
NAP
CS
19
20
RD
WRITE
21
BUSY
22, 23
24–28, 33–39
29
30, 31
32
40
41
R1, R2
D0–D11
DV
DD
DGND
V
DRIVE
D12
CONVST
42
RESET
43
44
45
MODE2
MODE1
CLIP
REV. 0
–5–
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