differential operation gives the lowest even-order harmonic
components. A lower input voltage of 3Vp-p or 2Vp-p can
also be selected using the internal references, further opti-
mizing SFDR. Alternatively, a single-ended input range can
be used by tying the IN input to the common-mode voltage
if desired.
The ADS852 also provides an over-range flag that indicates
when the input signal has exceeded the converter’s full-scale
range. This flag can also be used to reduce the gain of the
front end signal conditioning circuitry. It also employs
digital error correction techniques to provide excellent dif-
ferential linearity for demanding imaging applications. The
ADS852 is available in a small 48-lead TQFP package.
DESCRIPTION
The ADS852 is a high-dynamic range 14-bit, 65MHz
pipelined analog-to-digital converter. It includes a high-
bandwidth linear track/hold that gives excellent spurious
performance up to and beyond the Nyquist rate. This high-
bandwidth track/hold also has a low jitter of only 0.25pS
rms, leading to excellent SNR performance. The clock input
can accept a low level differential sine wave or square wave
signal down to 0.5Vp-p, further improving the SNR perfor-
mance. It also accepts a single-ended clock signal and has
flexible threshold levels.
The ADS852 has a 4Vp-p differential input range (2Vp-p x
2 inputs, +16dBm) for optimum signal-to-noise ratio. The
+V
S
CLK
ADS852
Timing Circuitry
CLK
2Vp-p
2Vp-p
IN
T/H
IN
14-Bit
Pipelined
A/D Core
Error
Correction
Logic
3-State
Outputs
D0
•
•
•
D13
CM
(+2.5V)
Reference Ladder
and Driver
Reference and
Mode Select
OVR
REFT
V
REF
SEL1 SEL2
REFB
OE VDRV
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
= full specified temperature range, differential input range = 1.5V to 3.5V, sampling rate = 65MHz, and external reference, unless otherwise noted.
ADS852Y
PARAMETER
POWER SUPPLY REQUIREMENTS
Supply Voltage: +V
S
Supply Current: +I
S
Output Driver Supply Current (VDRV)
Power Dissipation: VDRV = 5V
VDRV = 3V
Power Down
Thermal Resistance,
θ
JA
48-Lead TQFP
CONDITIONS
Operating
Operating
MIN
+4.75
TYP
+5.0
120
12
670
650
20
MAX
+5.25
UNITS
V
mA
mA
mW
mW
mW
°C/W
740
720
Operating
NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full Scale. (3) Two-tone
intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental
envelope. (4) A 50kΩ pull-down resistor is inserted internally. (5) Includes internal reference. (6) Excludes internal reference.
Analog Input ........................................................... (–0.3V) to (+V
S
+0.3V)
Logic Input ............................................................. (–0.3V) to (+V
S
+0.3V)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +150°C
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
ADS852Y
PACKAGE
48-Lead TQFP
PACKAGE
DRAWING
NUMBER
(1)
xxx
TEMPERATURE
RANGE
–40°C to +85°C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
3
ADS852
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O
DESIGNATOR
BYP
+V
S
+V
S
+V
S
GND
CLK
CLK
GND
GND
OVR
DV
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
Bypass Point
Supply Voltage
Supply Voltage
Supply Voltage
Ground
Clock Input
Complementary Clock Input
Ground
Ground
Overrange Indicator
Data Valid Pulse: HI = Data Vaild
Most Significant Bit (MSB)
Data Bit 12
Data Bit 11
Data Bit 10
Data Bit 9
Data Bit 8
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Least Significant Bit (LSB)
PIN
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I
I
I/O
DESIGNATOR
VDRV
GND
OE
PD
BTC
GND
SEL2
SEL1
V
REF
GND
GND
GND
GND
REFN
CM
REFP
GND
GND
IN
GND
IN
+V
S
+V
S
DESCRIPTION
Output Bit Driver Voltage Supply
Ground
Output Enable: HI = High Impedance;
LO or Floating: Normal Operation
Power Down: HI = Power Down; LO = Normal
HI = Binary Two’s Complement;
LO = Straight Binary
Ground
Reference Select 2: See Table
Reference Select 1: See Table
Internal Reference Voltage
Ground
Ground
Ground
Ground
Bottom Reference Voltage Bypass
Common-Mode Voltage (mid-scale)
Top Reference Voltage Bypass
Ground
Ground
Complementary Analog Input
Ground
Analog Input
Supply Voltage
Supply Voltage
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
PIN DIAGRAM
REFN
REFP
GND
GND
GND
GND
GND
+V
S
+V
S
48
BYP
+V
S
+V
S
+V
S
GND
CLK
CLK
GND
GND
1
2
3
4
5
6
7
8
9
47
46
45
44
43
42
41
40
CM
IN
IN
39
38
37
36 GND
35 GND
34 V
REF
33 SEL1
32 SEL2
ADS852Y
31 GND
30 BTC
29 PD
28 OE
27 GND
26 VDRV
25 D0 (LSB)
OVR 10
DV 11
D13 (MSB) 12
13
D12
14
D11
15
D10
16
D9
17
D8
18
D7
19
D6
20
D5
21
D4
22
D3
23
D2
24
D1
®
ADS852
4
TIMING DIAGRAM
N+1
Analog In
N
t
D
Clock
t
CONV
N+2
N+3
N+4
N+5
t
L
t
H
N+6
N+7
7 Clock Cycles
t
2
Data Out
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
t
1
Data Invalid
SYMBOL
t
CONV
t
L
t
H
t
D
t
1
t
2
DESCRIPTION
Convert Clock Period
Clock Pulse Low
Clock Pulse High
Aperture Delay
Data Hold Time, C
L
= 0pF
New Data Delay Time, C
L
= 15pF max
MIN
15.4
7.6
7.6
3.9
TYP
MAX
1µs
UNITS
ns
ns
ns
ns
ns
ns
t
CONV
/2
t
CONV
/2
3
12
TABLE, REFERENCE/FULL SCALE RANGE SELECT
DESIRED
FULL SCALE RANGE
4Vp-p (2Vp-p x 2, +16dBm)
3Vp-p (1.5Vp-p x 2, +13dBm)
2Vp-p (1Vp-p x 2, +10dBm)
SEL1
GND
GND
V
REF
SEL2
GND
+V
S
GND
INTERNAL
V
REF
2V
1.5V
1V
For External Reference Operation, tie V
REF
to +V
S
, the full scale range will be 2X the reference value. For instance, selecting a 2V External Reference will set
the full scale values of 1.5V to 3.5V for both IN and IN inputs.
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