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IN74LV138D

Description
3-to-8 line decoder/demultiplexer;inverting
Categorylogic    logic   
File Size87KB,8 Pages
ManufacturerINTEGRAL
Websitehttp://www.integral.by/english.phtml
Download Datasheet Parametric Compare View All

IN74LV138D Overview

3-to-8 line decoder/demultiplexer;inverting

IN74LV138D Parametric

Parameter NameAttribute value
MakerINTEGRAL
package instruction,
Reach Compliance Codeunknow
TECHNICAL DATA
IN74LV138
3-to-8 line decoder/demultiplexer;
inverting
The IN74LV138 is a low-voltage Si-gate CMOS device and is pin
and function compatible 74HCT138.
The74LV138 accepts three binary weighted address inputs -
(A
0
,A
1
,A
2
) and when enabled,provide 8 - mutually exclusive active
LOW outputs (Y
0
to Y
7
).
The “138” features three enable inputs: two active LOW (CS
2
,CS
3
and one active HIGH (CS
1
).Every output will be HIGH untess CS
2
, and
CS
3
are LOW and CS
1
is HIGH.
Optimized for Low Voltage applications:1.2 to 3.6 V
Demultiplexing capability
Multiple input enabte for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
Output capability: standard
16
1
16
1
D SUFFIX
SOIC
N SUFFIX
PLASTIC
ORDERING INFORMATION
IN74LV138N Plastic
IN74LV138D SOIC
T
A
= -40° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
CS1 CS2 CS3
X X H
X H X
L X X
PIN 16 =V
CC
PIN 8 = GND
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
A2 A1 A0
X X X
X X X
X X X
L L L
L L H
L H L
L H H
H L L
H L H
H H L
H H H
Outputs
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
H H H H H H H H
H H H H H H H H
H H H H H H H H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L H H H
H L H H
H H L H
H H H L
H = high level (steady state)
L = low level (steady state)
X = don’t care
INTEGRAL
1

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Description 3-to-8 line decoder/demultiplexer;inverting 3-to-8 line decoder/demultiplexer;inverting 3-to-8 line decoder/demultiplexer;inverting
Maker INTEGRAL - INTEGRAL
Reach Compliance Code unknow - unknow
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