DS1339
I
2
C Serial Real-Time Clock
GENERAL DESCRIPTION
The DS1339 serial real-time clock (RTC) is a low-
power clock/date device with two programmable time-
of-day alarms and a programmable square-wave
output. Address and data are transferred serially
2
through an I C bus. The clock/date provides seconds,
minutes, hours, day, date, month, and year
information. The date at the end of the month is
automatically adjusted for months with fewer than 31
days, including corrections for leap year. The clock
operates in either the 24-hour or 12-hour format with
AM/PM indicator. The DS1339 has a built-in power-
sense circuit that detects power failures and
automatically switches to the backup supply,
maintaining time, date, and alarm operation.
BENEFITS AND FEATURES
Completely Manages All Timekeeping
Functions
o
Real-Time Clock Counts Seconds,
Minutes, Hours, Date of the Month,
Month, Day of the Week, and Year
with Leap-Year Compensation Valid
Up to 2100
o
Two Time-of-Day Alarms
o
Programmable Square-Wave Output
o
Oscillator Stop Flag
Interfaces to Most Microcontrollers
o
I
2
C Serial Interface
Low-Power Operation Extends Battery
Backup Run Time
o
Automatic Power-Fail Detect and
Switch Circuitry
o
Trickle-Charge Capability
Underwriters Laboratories® (UL)
Recognized
Surface-Mount Package with an
Integrated Crystal (DS1339C Saves
Additional Space and Simplifies Design
APPLICATIONS
Handhelds (GPS, POS Terminals)
Consumer Electronics (Set-Top Box, Digital
Recording, Network Appliance)
Office Equipment (Fax/Printers, Copier)
Medical (Glucometer, Medicine Dispenser)
Telecommunications (Routers, Switches, Servers)
Other (Utility Meter, Vending Machine, Thermostat,
Modem
)
Pin Configurations appear at end of data sheet.
ORDERING INFORMATION
PART
DS1339C-2#
DS1339C-3#
DS1339C-33#
DS1339U-2+
DS1339U-3+
DS1339U-33+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
VOLTAGE (V)
2.0
3.0
3.3
2.0
3.0
3.3
PIN-PACKAGE
16 SO (300 mils)
16 SO (300 mils)
16 SO (300 mils)
8
µSOP
8
µSOP
8
µSOP
TOP MARK†
DS1339C-2
DS1339C-3
DS1339C-33
1339 rr-2
1339 rr-3
1339 rr-33
+Denotes
a lead(Pb)-free/RoHS-compliant package.
#Denotes a RoHS-compliant device that may include lead that is exempt under the RoHS requirements. The lead finish is JESD97 category
e3, and is compatible with both lead-based and lead-free soldering processes.
†A
“+” anywhere on the top mark indicates a lead(Pb)-free device. A “#” denotes a RoHS-compliant device. rr
=
second line, revision code
19-5770; Rev 3/15
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DS1339 I C Serial Real-Time Clock
2
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground………………………………………………………………-0.3V to +6.0V
Operating Temperature Range (Noncondensing)………………………………………………………….-40°C to +85°C
Storage Temperature Range………………………………………………………………………………..-55°C to +125°C
Lead Temperature (soldering, 10s)...…………………………………………………………………………………+260°C
Soldering Temperature (reflow).……………………………………………………………………………………….+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
µSOP
Junction-to-Ambient Thermal Resistance (θ
JA
).…………………...……………………………………….206.3°C/W
Junction-to-Case Thermal Resistance (θ
JC
)……………………………………………………………………42°C/W
SO
Junction-to-Ambient Thermal Resistance (θ
JA
).……………………………………………………………….73°C/W
Junction-to-Case Thermal Resistance (θ
JC
)……………………………………………………………………23°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maxim-ic.com/thermal-tutorial.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= -40°C to +85°C) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
DS1339-2
Supply Voltage
V
CC
V
BACKUP
V
IH
V
IL
DS1339-2
Power-Fail Voltage
V
PF
DS1339-3
DS1339-33
DS1339-3
DS1339-33
Backup Supply Voltage
Logic 1
Logic 0
MIN
1.8
2.7
2.97
1.3
0.7 x
V
CC
-0.3
1.58
2.45
2.70
1.70
2.59
2.85
TYP
2.0
3.0
3.3
3.0
MAX
5.5
5.5
5.5
3.7
V
CC
+
0.3
+0.3 x
V
CC
1.80
2.70
2.97
V
V
V
V
V
UNITS
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DS1339 I C Serial Real-Time Clock
2
DC ELECTRICAL CHARACTERISTICS
(V
CC
= MIN to MAX, T
A
= -40°C to +85°C.) (Note 2)
PARAMETER
Input Leakage
I/O Leakage
Logic 0 Out
V
OL
= 0.4V; V
CC
> V
CC
MIN (-3, -33);
V
CC
≥ 2.0V (-2)
Logic 0 Out
V
OL
= 0.2 (V
CC
);
1.8V < V
CC
< 2.0V (DS1339-2)
Logic 0 Out
V
OL
= 0.2 (V
CC
);
1.3V < V
CC
< 1.8V (DS1339-2)
V
CC
Active Current
SYMBOL
I
LI
I
LO
I
OL
CONDITIONS
(Note 3)
(Note 4)
(Note 4)
MIN
TYP
MAX
1
1
3
UNITS
µA
µA
mA
I
OL
(Note 4)
3
mA
I
OL
I
CCA
(Note 4)
(Note 5)
-2: V
CC
= 2.2V
60
80
250
450
100
150
200
250
2000
4000
25
100
µA
µA
µA
V
CC
Standby Current (Note 6)
I
CCS
-3: V
CC
= 3.3V
-33: V
CC
= 5.5V
Trickle-Charger Resistor Register
10h = A5h, V
CC
= Typ, V
BACKUP
= 0V
Trickle-Charger Resistor Register
10h = A6h, V
CC
= Typ, V
BACKUP
= 0V
Trickle-Charger Resistor Register
10h = A7h, V
CC
= Typ, V
BACKUP
= 0V
V
BACKUP
Leakage Current
R1
R2
R3
I
BKLKG
(Note 7)
Ω
Ω
Ω
nA
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 0V, T
A
= -40°C to +85°C.)
(Note 2)
PARAMETER
V
BACKUP
Current
EOSC
= 0, SQW Off
V
BACKUP
Current
EOSC
= 0, SQW On
V
BACKUP
Current
EOSC
= 1
SYMBOL
I
BKOSC
I
BKSQW
I
BKDR
CONDITIONS
(Note 8)
(Note 8)
MIN
TYP
400
600
10
MAX
700
1000
100
UNITS
nA
nA
nA
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DS1339 I C Serial Real-Time Clock
2
AC ELECTRICAL CHARACTERISTICS
(V
CC
= MIN to MAX, T
A
= -40°C to +85°C.) (Note 9)
PARAMETER
SCL Clock Frequency
Bus Free Time Between a STOP
and START Condition
Hold Time (Repeated) START
Condition (Note 10)
LOW Period of SCL Clock
SYMBOL
f
SCL
CONDITION
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0.6
4.7
0
0
100
250
20 + 0.1C
B
20 + 0.1C
B
20 + 0.1C
B
20 + 0.1C
B
0.6
4.0
400
(Note 9)
(Note 15)
100
10
300
1000
300
300
0.9
MIN
100
TYP
MAX
400
kHz
100
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
pF
pF
ms
UNITS
t
BUF
t
HD:STA
t
LOW
t
HIGH
HIGH Period of SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time (Notes 11, 12)
Data Setup Time (Note 13)
Rise Time of Both SDA and SCL
Signals (Note 14)
Fall Time of Both SDA and SCL
Signals (Note 14)
Setup Time for STOP Condition
Capacitive Load for Each Bus
Line (Note 14)
I/O Capacitance (SDA, SCL)
Oscillator Stop Flag (OSF) Delay
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
C
B
C
I/O
t
OSF
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DS1339 I C Serial Real-Time Clock
2
POWER-UP/DOWN CHARACTERISTICS
(T
A
= -40°C to +85°C) (Note 2,
Figure 1)
PARAMETER
Recovery at Power-Up
V
CC
Fall Time; V
PF(MAX)
to V
PF(MIN)
V
CC
Rise Time; V
PF(MIN)
to V
PF(MAX)
SYMBOL
t
REC
t
VCCF
t
VCCR
CONDITIONS
(Note 16)
300
0
MIN
TYP
MAX
2
UNITS
ms
µs
µs
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in
battery-backup mode.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Limits at -40°C are guaranteed by design and are not production tested.
SCL only.
SDA and SQW/INT.
I
CCA
—SCL at f
SC
max, V
IL
= 0.0V, V
IH
= V
CC
, trickle charger disabled.
Specified with the I
2
C bus inactive, V
IL
= 0.0V, V
IH
= V
CC
, trickle charger disabled.
V
CC
must be less than 3.63V if the 250Ω resistor is selected.
Using recommended crystal on X1 and X2.
Guaranteed by design; not production tested.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IHMIN
of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
The maximum t
HD:DAT
need only be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
≥
to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
R(MAX)
+ t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line
is released.
C
B
—total capacitance of one bus line in pF.
The parameter t
OSF
is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V
≤
V
CC
≤
V
CCMAX
and 1.3V
≤
V
BACKUP
≤
3.7V.
This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay occurs.
Note 14:
Note 15:
Note 16:
Figure 1. Power-Up/Down Timing
V
CC
V
PF(MAX)
V
PF(MIN)
t
VCCF
t
VCCR
t
REC
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
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