DS1338
I
2
C RTC with 56-Byte NV RAM
GENERAL DESCRIPTION
The DS1338 serial real-time clock (RTC) is a low-
power, full binary-coded decimal (BCD)
clock/calendar plus 56 bytes of NV SRAM. Address
and data are transferred serially through an I
2
C
interface. The clock/calendar provides seconds,
minutes, hours, day, date, month, and year
information. The end of the month date is
automatically adjusted for months with fewer than 31
days, including corrections for leap year. The clock
operates in either the 24-hour or 12-hour format with
AM/PM indicator. The DS1338 has a built-in power-
sense circuit that detects power failures and
automatically switches to the backup supply,
maintaining time and date operation
BENEFITS AND FEATURES
•
Completely Manages All Timekeeping
Functions
o
RTC Counts Seconds, Minutes, Hours,
Date of the Month, Month, Day of the
Week, and Year with Leap-Year
Compensation Valid Up to 2100
o
56-Byte, Battery-Backed, General-
Purpose RAM with Unlimited Writes
o
Programmable Square-Wave Output
Signal
Surface-Mount Package with an Integrated
Crystal (DS1338C) Saves Additional Space
and Simplifies Design
Interfaces with Most Microcontrollers
o
I
2
C Serial Interface
Low-Power Operation Extends Battery
Backup Run Time
o
Automatic Power-Fail Detect and Switch
Circuitry
-40°C to +85°C Industrial Temperature Range
Supports Operation in a Wide Range of
Applications
Underwriters Laboratories (UL®) Recognized
•
•
APPLICATIONS
Handhelds (GPS, POS Terminal)
Consumer Electronics (Set-Top Box, Digital
Recording, Network Appliance)
Office Equipment (Fax/Printer, Copier)
Medical (Glucometer, Medicine Dispenser)
Telecommunications (Router, Switcher, Server)
Other (Utility Meter, Vending Machine, Thermostat,
Modem)
•
•
•
UL is a registered trademark of Underwriters Laboratories Inc.
ORDERING INFORMATION
PART
DS1338Z-18+
DS1338Z-3+
DS1338Z-33+
DS1338U-18+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 SO (0.150″)
8 SO (0.150″)
8 SO (0.150″)
8
µSOP
8
µSOP
8
µSOP
TOP MARK†
DS1338-18
DS1338-3
DS133833
1338
rr-18
1338
rr-3
1338
rr-33
DS1338C-18
DS1338C-3
DS1338C-33
TYPICAL OPERATING CIRCUIT
R
PU
= t
r
/C
b
V
CC
CRYSTAL
R
PU
V
CC
DS1338U-3+
DS1338U-33+
X1
SCL
X2
V
CC
SQW/OUT
i
V
CC
R
PU
CPU
SDA
DS1338
V
BAT
GND
Pin Configurations appear at end of data sheet.
DS1338C-18#
-40°C to +85°C
16 SO (0.300″)
DS1338C-3#
-40°C to +85°C
16 SO (0.300″)
DS1338C-33#
-40°C to +85°C
16 SO (0.300″)
rr = second line, revision level
+ Denotes a lead(Pb)-free/RoHS-compliant device.
# Denotes a RoHS-compliant device that may include lead that is
exempt under the RoHS requirements. The lead finish is JESD97
category e3, and is compatible with both lead-based and lead-free
soldering processes.
†
A “+” anywhere on the top mark denotes a lead-free device. A “#”
denotes a RoHS-compliant device.
19-6019; Rev 4/15
1 of 16
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground………………………………………………………..……..-0.3V to +6.0V
Operating Temperature Range…………………………………………………………………………..……-40°C to +85°C
Storage Temperature Range………………………………………………………………………………...-55°C to +125°C
Lead Temperature (soldering, 10s) ……….………………………………………………………………………. +260°C
Soldering Temperature (reflow) ……………………………………………………………………………………. +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(V
CC
= V
CC(MIN)
to V
CC(MAX)
, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C, unless
otherwise noted.) (Note 1)
PARAMETER
Supply Voltage
Logic 1
Logic 0
Power-Fail Voltage
V
BAT
Input Voltage
SYMBOL
V
CC
V
IH
V
IL
V
PF
V
BAT
CONDITIONS
DS1338-18
DS1338-3
DS1338-33
(Note 2)
(Note 2)
DS1338-18
DS1338-3
DS1338-33
(Note 2)
MIN
1.71
2.7
3.0
0.7 x
V
CC
-0.3
1.51
2.45
2.70
1.3
1.62
2.59
2.82
3.0
TYP
1.8
3.0
3.3
MAX
5.5
5.5
5.5
V
CC
+
0.3
+0.3 x
V
CC
1.71
2.70
2.97
3.7
UNITS
V
V
V
V
V
DC ELECTRICAL CHARACTERISTICS
(V
CC
= V
CC(MIN)
to V
CC(MAX)
, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= TYP,
T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
Input Leakage
I/O Leakage
SDA Logic 0 Output
SYMBOL
I
LI
I
LO
I
OLSDA
CONDITIONS
(Note 3)
(Note 4)
V
CC
> 2V; V
OL
= 0.4V
V
CC
< 2V; V
OL
= 0.2 x V
CC
V
CC
> 2V; V
OL
= 0.4V
1.71V < V
CC
< 2V;
V
OL
= 0.2 x V
CC
1.3V < V
CC
< 1.71V;
V
OL
= 0.2 x V
CC
DS1338-18: V
CC
= 1.89V
DS1338-3:
V
CC
= 3.30V
V
CC
= 3.63V
DS1338-33
V
CC
= 5.5V
DS1338-18: V
CC
= 1.89V
DS1338-3:
V
CC
= 3.30V
V
CC
= 3.63V
DS1338-33
V
CC
= 5.5V
MIN
TYP
MAX
1
1
3.0
3.0
3.0
3.0
250
75
110
120
60
80
85
25
150
200
200
325
100
125
125
200
100
mA
µA
µA
UNITS
µA
µA
mA
SQW/OUT Logic 0 Output
I
OLSQW
Active Supply Current
(Note 5)
I
CCA
Standby Current (Note 6)
V
BAT
Leakage Current
(V
CC
Active)
I
CCS
µA
I
BATLKG
nA
2 of 16
DS1338
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 0V, T
A
= -40°C to +85°C,
unless otherwise noted. Typical values are at V
BAT
= 3.0V, T
A
= +25°C, unless
otherwise noted.) (Note 1)
PARAMETER
V
BAT
Current (OSC ON); V
BAT
= 3.7V, SQW/OUT OFF (Note 7)
V
BAT
Current (OSC ON); V
BAT
= 3.7V, SQW/OUT ON (32kHz)
(Note 7)
V
BAT
Data-Retention Current (Osc Off); V
BAT
= 3.7V (Note 7)
SYMBOL
I
BATOSC1
I
BATOSC2
I
BATDAT
MIN
TYP
800
1025
10
MAX
1200
1400
100
UNITS
nA
nA
nA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= V
CC(MIN)
to V
CC(MAX)
, T
A
= -40°C to +85°C) (Note 1)
PARAMETER
SCL Clock Frequency
Bus Free Time Between STOP
and START Condition
Hold Time (Repeated) START
Condition (Note 8)
LOW Period of SCL Clock
SYMBOL
f
SCL
t
BUF
t
HD:STA
CONDITION
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Data Setup Time (Note 11)
Rise Time of Both SDA and
SCL Signals (Note 12)
Fall Time of Both SDA and
SCL Signals (Note 12)
Setup Time for STOP
Condition
Capacitive Load for Each Bus
Line
I/O Capacitance (SDA, SCL)
Oscillator Stop Flag (OSF)
Delay
t
SU:DAT
Standard mode
Fast mode
t
R
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
(Note 12)
(Note 13)
(Note 14)
100
MIN
100
0
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0.6
4.7
0
0
100
250
20 + 0.1C
B
20 + 0.1C
B
20 + 0.1C
B
20 + 0.1C
B
0.6
4.0
400
10
300
1000
300
300
ns
ns
0.9
TYP
MAX
400
100
UNITS
kHz
µs
µs
µs
µs
µs
µs
t
LOW
HIGH Period of SCL Clock
Setup Time for Repeated
START Condition
Data Hold Time (Notes 9, 10)
t
HIGH
t
SU:STA
t
HD:DAT
t
F
t
SU:STO
C
B
C
I/O
t
OSF
ns
µs
pF
pF
ms
3 of 16
DS1338
POWER-UP/POWER-DOWN CHARACTERISTICS
(T
A
= -40°C to +85°C) (Note 1, Figure 1)
PARAMETER
Recovery at Power-Up (Note 15)
V
CC
Fall Time; V
PF(MAX)
to V
PF(MIN)
V
CC
Rise Time; V
PF(MIN)
to V
PF(MAX)
SYMBOL
t
REC
t
VCCF
t
VCCR
300
0
MIN
TYP
MAX
2
UNITS
ms
µs
µs
Warning: Negative undershoots below -0.3V while the part is in battery-backed mode may cause
loss of data.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Limits at -40°C are guaranteed by design and not production tested.
All voltages are referenced to ground.
SCL only.
SDA and SQW/OUT.
I
CCA
—SCL clocking at max frequency = 400kHz.
Specified with the I
2
C bus inactive.
Measured with a 32.768kHz crystal attached to X1 and X2.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH(MIN)
of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
The maximum t
HD:DAT
need only be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
≥ to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
R(MAX)
+ t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line
is released.
C
B
—total capacitance of one bus line in pF.
Guaranteed by design. Not production tested.
The parameter t
OSF
is the time period the oscillator must be stopped for the OSF flag to be set over the voltage range of
0.0V ≤ V
CC
≤ V
CC(MAX)
and 1.3V ≤ V
BAT
≤ 3.7V.
This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay occurs.
Note 12:
Note 13:
Note 14:
Note 15:
Figure 1. Power-Up/Power-Down Timing
V
CC
V
PF(MAX)
V
PF(MIN)
t
VCCF
t
VCCR
t
REC
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
4 of 16
DS1338
Figure 2. Timing Diagram
Figure 3. Block Diagram
SQW/OUT
X1
C
L
1Hz/4.096kHz/8.192kHz/32.768kHz
MUX/
BUFFER
N
1Hz
X2
"C" VERSION ONLY
C
L
Oscillator
and divider
CONTROL
LOGIC
POWER
CONTROL
RAM
(56 X 8)
V
CC
GND
V
BAT
DS1338
SCL
SDA
SERIAL BUS
INTERFACE
AND ADDRESS
REGISTER
CLOCK,
CALENDAR,
AND CONTROL
REGISTERS
USER BUFFER
(7 BYTES)
5 of 16
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