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70T3339S133BF

Description
SRAM 512K X 18 DP
Categorystorage    storage   
File Size329KB,28 Pages
ManufacturerIDT (Integrated Device Technology)
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70T3339S133BF Overview

SRAM 512K X 18 DP

70T3339S133BF Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeCABGA
package instructionTFBGA, BGA208,17X17,32
Contacts208
Manufacturer packaging codeBF208
Reach Compliance Codenot_compliant
ECCN code3A991.B.2.A
Samacsys DescriptionCHIP ARRAY BGA 15.0 X 15.0 MM X 0.8 MM P
Maximum access time15 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)133 MHz
I/O typeCOMMON
JESD-30 codeS-PBGA-B208
JESD-609 codee0
length15 mm
memory density9437184 bit
Memory IC TypeDUAL-PORT SRAM
memory width18
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals208
word count524288 words
character code512000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX18
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Encapsulate equivalent codeBGA208,17X17,32
Package shapeSQUARE
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply2.5,2.5/3.3 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum standby current0.015 A
Minimum standby current2.4 V
Maximum slew rate0.37 mA
Maximum supply voltage (Vsup)2.6 V
Minimum supply voltage (Vsup)2.4 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn63Pb37)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width15 mm
HIGH-SPEED 2.5V
IDT70T3339/19/99S
512/256/128K X 18
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features:
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– Data input, address, byte enable and control registers
– 1.5ns setup to clock and 0.5ns hold on all control, data,
and address inputs @ 200MHz
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine
pitch Ball Grid Array (fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Functional Block Diagram
UB
L
LB
L
UB
R
LB
R
FT/PIPE
L
1/0
0a 1a
a
0b 1b
b
1b 0b
b
1a 0a
a
1/0
FT/PIPE
R
R/W
L
CE
0L
CE
1L
1
0
1/0
B B
WW
0 1
L L
B B
WW
1 0
R R
1
0
1/0
R/W
R
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
R
1b 0b 1a 0a
FT/PIPE
L
0/1
0a 1a 0b
1b
,
0/1
FT/PIPE
R
ab
512/256/128K x 18
MEMORY
ARRAY
ba
I/O
0L
- I/O
17L
Din_L
Din_R
I/O
0R
- I/O
17R
CLK
L
A
18L
(1)
A
0L
REPEAT
L
ADS
L
CNTEN
L
A
18R
(1)
CLK
R
,
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
REPEAT
R
ADS
R
CNTEN
R
TDI
TCK
TMS
TRST
CE
0 L
CE1L
R/
W
L
INTERRUPT
COLLISION
DETECTION
LOGIC
CE
0 R
CE1 R
R/
W
R
JTAG
TDO
COL
L
INT
L
ZZ
L
(2)
COL
R
INT
R
ZZ
CONTROL
LOGIC
ZZ
R
(2)
5652 drw 01
NOTES:
1. Address A
18
is a NC for the IDT70T3319. Also, Addresses A
18
and A
17
are NC's for the IDT70T3399.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and
OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
FEBRUARY 2018
DSC-5652/9
1
©2018 Integrated Device Technology, Inc.
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