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74HC112D,652

Description
Flip Flops DUAL J-K NEG EDGE
Categorylogic    logic   
File Size774KB,20 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
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74HC112D,652 Overview

Flip Flops DUAL J-K NEG EDGE

74HC112D,652 Parametric

Parameter NameAttribute value
Brand NameNXP Semiconductor
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeSOP
package instructionPLASTIC, SOT-108, SO-14
Contacts16
Manufacturer packaging codeSOT109-1
Reach Compliance Codecompliant
seriesHC/UH
JESD-30 codeR-PDSO-G16
length9.9 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeJ-K FLIP-FLOP
Maximum Frequency@Nom-Sup20000000 Hz
MaximumI(ol)0.004 A
Humidity sensitivity level1
Number of digits2
Number of functions2
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
power supply2/6 V
propagation delay (tpd)265 ns
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)4.5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNICKEL/PALLADIUM/GOLD (NI/PD/AU)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
Trigger typeNEGATIVE EDGE
width3.9 mm
minfmax24 MHz
74HC112; 74HCT112
Dual JK flip-flop with set and reset; negative-edge trigger
Rev. 3 — 9 August 2016
Product data sheet
1. General description
The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features
individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has
complementary nQ and nQ outputs. The set and reset are asynchronous active LOW
inputs and operate independently of the clock input. The J and K inputs control the state
changes of the flip-flops as described in the mode select function table. The J and K
inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for
predictable operation. Inputs include clamp diodes that enable the use of current limiting
resistors to interface inputs to voltages in excess of V
CC
.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features and benefits
Input levels:
For 74HC112: CMOS level
For 74HCT112: TTL level
Asynchronous set and reset
Specified in compliance with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC112D
74HCT112D
74HC112DB
74HCT112DB
74HC112PW
74HCT112PW
40 C
to +125
C
40 C
to +125
C
SSOP16
plastic shrink small outline package; 16 leads; body width
5.3 mm
SOT338-1
SOT403-1
40 C
to +125
C
Name
SO16
Description
Version
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Type number
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
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