531NA580M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > oscillator> 531NA580M000DG

531NA580M000DG: DescriptionLVDS Output Clock Oscillator, 580MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; Categoryoscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531NA580M000DG Overview

LVDS Output Clock Oscillator, 580MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531NA580M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Is Samacsys	N
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	580 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Adjustable output voltage regulator circuit diagram

Differential driver circuit diagram for voltage output DAC AD5620

SAA1250 (TV) infrared remote control transmitter circuit

Electrical schematic diagram of B2012A gantry planer (2)

Southern Hi-tech 70 mobile phone repair diagram 2

810 computer motherboard circuit diagram_32

[Original] FPGA Development Notes--Keystrokes: [i=s] This post was last edited by chun912 on 2017-5-15 16:05 [/i] [b]Article Abstract: [/b] This article mainly describes the key processing mode and ideas (sampling) based on FPGA. It seems to be a ...; chun912 FPGA/CPLD

I would like to ask an expert, there is a boot sound when wince starts, but after startup, there is no sound when playing MP3 and some system sounds.: As title...; limingjing1986 Embedded System

Who wants to apply for the LM3S8962 development board? Hurry up and take your place!: Due to the October event: https://bbs.eeworld.com.cn/thread-183827-1-13.htmlThe trial period is two months, and ends at the end of December, so there may be about 10 boards that can continue to be cyc...; EEWORLD社区 Microcontroller MCU

The 430 modules I plan to buy are SENSE1 and SHARP96: If you are interested in buying, please contact QQ: 33225九九215...; 硕果累累 Microcontroller MCU

Are there any syntax errors when defining pointers and references to bit variables in C51? Do I need to use absolute addresses to assign values?: Several bit variables are defined: sbit CA = P3^5; sbit FA = P3^4; sbit CB = P3^2; sbit FB = P3^3; Because the program needs to be compressed, the values were previously assigned by several functions,...; whbahx Embedded System

Urgent question about the circuit implementation principle of digital filter: For digital filters, after obtaining the H(z) filter function, how to implement it with hardware in actual application? Is it implemented with LC circuit using the method of designing analog filters? ...; rwlggd Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components