NCV7340
High Speed Low Power CAN
Transceiver
Description
The NCV7340 CAN transceiver is the interface between a
controller area network (CAN) protocol controller and the physical
bus and may be used in both 12 V and 24 V systems. The transceiver
provides differential transmit capability to the bus and differential
receive capability to the CAN controller.
The NCV7340 is a new addition to the CAN high−speed transceiver
family and is an improved drop−in replacement for the AMIS−42665.
Due to the wide common−mode voltage range of the receiver inputs,
the NCV7340 is able to reach outstanding levels of electromagnetic
susceptibility (EMS). Similarly, extremely low electromagnetic
emission (EME) is achieved by the excellent matching of the output
signals.
Features
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MARKING
DIAGRAM
8
8
1
SOIC−8
CASE 751AZ
NV7340−x
FALYW
G
G
1
•
Compatible with the ISO 11898 Standard (ISO 11898−2, ISO
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
11898−5 and SAE J2284)
Low Quiescent Current
High Speed (up to 1 Mbps)
Ideally Suited for 12 V and 24 V Industrial and Automotive
Applications
Extremely Low Current Standby Mode with Wakeup via the Bus
Low EME Common−Mode Choke is No Longer Required
Voltage Source via V
SPLIT
Pin for Stabilizing the Recessive Bus
Level (Further EMC Improvement)
No Disturbance of the Bus Lines with an Un−powered Node
Transmit Data (TxD) Dominant Time−out Function
Thermal Protection
Bus Pins Protected Against Transients in an Automotive
Environment
Bus and V
SPLIT
Pins Short−Circuit Proof to Supply Voltage and
Ground
Logic Level Inputs Compatible with 3.3 V Devices
Up to 110 Nodes can be Connected to the Same Bus in Function of
Topology
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These are Pb−Free Devices
NV7340− = Specific Device Code
x = 3 (NCV7340D13R2G)
= 2 (NCV7340D12R2G)
= 4 (NCV7340D14R2G)
F
= Fab Location Code*
*For NCV7340D14R2G only
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
PIN ASSIGNMENT
1
TxD
2
NCV7340
GND
3
V
CC
4
RxD
NCV7340DxxR2G
(Top View)
7
CANH
6
CANL
5
V
SPLIT
8
STB
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Typical Applications
•
Automotive
•
Industrial Networks
©
Semiconductor Components Industries, LLC, 2014
1
October, 2014 − Rev. 8
Publication Order Number:
NCV7340/D
NCV7340
Table 1. KEY TECHNICAL CHARACTERISTICS AND OPERATING RANGES
Symbol
V
CC
V
STB
V
TxD
V
RxD
V
CANH
V
CANL
V
SPLIT
V
O(dif)(bus_dom)
CM−range
C
load
t
pd(rec−dom)
t
pd(dom−rec)
T
J
Parameter
Power supply voltage
DC voltage at pin STB
DC voltage at pin TxD
DC voltage at pin RxD
DC voltage at pin CANH
DC voltage at pin CANL
DC voltage at pin V
SPLIT
Differential bus output voltage in
dominant state
Input common−mode range for
comparator
Load capacitance on IC outputs
Propagation delay TxD to RxD
Propagation delay TxD to RxD
Junction temperature
See Figure 7
See Figure 7
60
60
−40
0 < V
CC
< 5.25 V; no time limit
0 < V
CC
< 5.25 V; no time limit
0 < V
CC
< 5.25 V; no time limit
42.5
W
< R
LT
< 60
W
Guaranteed differential receiver threshold
and leakage current
Conditions
Min
4.75
0
0
0
−50
−50
−40
1.5
−35
Max
5.25
V
CC
V
CC
V
CC
+50
+50
+40
3
+35
15
230
245
150
Unit
V
V
V
V
V
V
V
V
V
pF
ns
ns
°C
BLOCK DIAGRAM
V
CC
3
VCC
NCV7340
7
TxD
1
Timer
VCC
CANH
V
SPLIT
CANL
Thermal
shutdown
VCC
V
SPLIT
5
STB
8
Mode &
wakeup
control
Driver
control
6
RxD
GND
4
Wakeup
Filter
COMP
2
COMP
Figure 1. Block Diagram
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NCV7340
TYPICAL APPLICATION
Application Schematics
VBAT
IN
5V−reg
OUT
V
CC
STB
8
3
7
V
CC
R
LT
= 60
W
CANH
5
NCV7340
CAN
controller
RxD
4
V
SPLIT
C
LT
= 47 nF
CAN
BUS
TxD
1
6
2
CANL
R
LT
= 60
W
GND
GND
Figure 2. Application Diagram
Pin Description
TxD
GND
VCC
RxD
1
2
3
4
8
7
6
5
STB
CANH
CANL
V
SPLIT
Figure 3. NCV7340 Pin Assignment
NCV7340
Table 2. PIN FUNCTION DESCRIPTION
Pin
1
2
3
4
5
6
7
8
Name
TxD
GND
VCC
RxD
V
SPLIT
CANL
CANH
STB
Description
Transmit data input; low input
→
dominant driver; internal pullup current
Ground
Supply voltage
Receive data output; dominant transmitter
→
low output
Common−mode stabilization output
Low−level CAN bus line (low in dominant mode)
High−level CAN bus line (high in dominant mode)
Standby mode control input
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NCV7340
FUNCTIONAL DESCRIPTION
Operating Modes
NCV7340 provides two modes of operation as illustrated
in Table 3. These modes are selectable through pin STB.
Table 3. OPERATING MODES
Pin
STB
Low
High
Pin RXD
Mode
Normal
Standby
Low
Bus dominant
Wakeup request
detected
High
Bus recessive
No wakeup
request detected
Split Circuit
The V
SPLIT
pin is operational only in normal mode. In
standby mode this pin is floating. The V
SPLIT
can be
connected as shown in Figure 2 or, if it’s not used, can be left
floating. Its purpose is to provide a stabilized DC voltage of
0.5 x V
CC
to the bus avoiding possible steps in the
common−mode signal therefore reducing EME. These
unwanted steps could be caused by an un−powered node on
the network with excessive leakage current from the bus that
shifts the recessive voltage from its nominal 0.5 x V
CC
voltage.
Wakeup
When a valid wakeup (dominant state longer than t
Wake
)
is received during the standby mode the RxD pin is driven
low. The wakeup detection is not latched: RxD returns to
High state after t
wakedr
when the bus signal is released back
to recessive – see Figure 4. Wake−up behavior in case of a
permanent dominant − due to, for example, a bus short −
represents the only difference between the circuit functional
sub−versions listed in the Ordering Information table. When
the standby mode is entered while a dominant is present on
the bus, the “unconditioned bus wake−up” versions will
signal a bus−wakeup immediately after the state transition
(signal RxD
1
in Figure 4). The other version will signal
bus−wakeup only after the initial dominant is released
(signal RxD
2
in Figure 4). In this way it’s ensured, that a
CAN bus can be put to a low−power mode even if the nodes
have a level sensitivity to RxD pin and a permanent
dominant is present on the bus.
>t
Wake
<t
Wake
Normal Mode
In the normal mode, the transceiver is able to
communicate via the bus lines. The signals are transmitted
and received to the CAN controller via the pins TxD and
RxD. The slopes on the bus lines outputs are optimized to
give extremely low EME.
Standby Mode
In standby mode both the transmitter and receiver are
disabled and a very low−power differential receiver
monitors the bus lines for CAN bus activity. The bus lines
are terminated to ground and supply current is reduced to a
minimum, typically 10
mA.
When a wake−up request is
detected by the low−power differential receiver, the signal
is first filtered and then verified as a valid wake signal after
a time period of t
dwakerd
, the RxD pin is driven low by the
transceiver to inform the controller of the wake−up request.
CANH
CANL
STB
RxD2
(NCV7340−4)
RxD1
(NCV7340−2, 3)
t
dwakerd
t
Wake(RxD)
t
dwakedr
normal
standby
time
Figure 4. NCV7340 Wakeup Behavior
Overtemperature Detection
A thermal protection circuit protects the IC from damage
by switching off the transmitter if the junction temperature
exceeds a value of approximately 160°C. Because the
transmitter dissipates most of the power, the power
dissipation and temperature of the IC is reduced. All other
IC functions continue to operate. The transmitter off−state
resets when the temperature decreases below the shutdown
threshold and pin TxD goes high. The thermal protection
circuit is particularly needed when a bus line short circuits.
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NCV7340
TxD Dominant Time−out Function
Fail Safe Features
A TxD dominant time−out timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if pin TxD is forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on pin TxD exceeds the
internal timer value t
dom(TxD)
, the transmitter is disabled,
driving the bus into a recessive state. The timer is reset by a
positive edge on pin TxD.
This TxD dominant time−out time (t
dom(TxD)
) defines the
minimum possible bit rate to 40 kbps.
A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit to
either positive or negative supply voltage, although power
dissipation increases during this fault condition.
The pins CANH and CANL are protected from
automotive electrical transients (according to ISO 7637; see
Figure 5). Pins TxD and STB are pulled high internally
should the input become disconnected. Pins TxD, STB and
RxD will be floating, preventing reverse supply should the
V
CC
supply be removed.
ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GND (Pin 2). Positive currents flow into the IC. Sinking current means the current is flowing
into the pin; sourcing current means the current is flowing out of the pin.
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
CANH
V
CANL
V
SPLIT
V
TxD
V
RxD
V
STB
V
esd
Supply voltage
DC voltage at pin CANH
DC voltage at pin CANL
DC voltage at pin V
SPLIT
DC voltage at pin TxD
DC voltage at pin RxD
DC voltage at pin STB
Electrostatic discharge voltage at all pins
Electrostatic discharge voltage at CANH and CANL pins
V
schaff
Latchup
T
stg
T
A
T
J
Transient voltage, see Figure 5
Static latchup at all pins
Storage temperature
Ambient temperature
Maximum junction temperature
Note 1
Note 2
Note 3
Note 5
Note 4
−55
−40
−40
0 < V
CC
< 5.25 V; no time limit
0 < V
CC
< 5.25 V; no time limit
0 < V
CC
< 5.25 V; no time limit
Parameter
Conditions
Min
−0.3
−50
−50
−40
−0.3
−0.3
−0.3
−6
−500
−12
−150
Max
+6
+50
+50
+40
6
6
6
6
500
12
100
120
+150
+125
+170
Unit
V
V
V
V
V
V
V
kV
V
kV
V
mA
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 kW resistor.
2. Standardized charged device model ESD pulses when tested according to ESD−STM5.3.1−1999.
3. System human body model electrostatic discharge (ESD) pulses. Equivalent to discharging a 150 pF capacitor through a 330
W
resistor.
4. Static latchup immunity: Static latchup protection level when tested according to EIA/JESD78.
5. Pulses 1, 2a, 3a and 3b according to ISO 7637 part 3. Verification by external test house.
Table 5. THERMAL CHARACTERISTICS
Symbol
R
qJA_1
R
qJA_2
Parameter
Thermal Resistance Junction−to−Air, 1S0P PCB (Note 6)
Thermal Resistance Junction−to−Air, 2S2P PCB (Note 7)
Conditions
Free air
Free air
Value
125
75
Unit
K/W
K/W
6. Test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.
7. Test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage.
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