DS1005S-250+T&R datasheet, PDF

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DS1005S-250+T&R: DescriptionDelay Lines / Timing Elements; Categorylogic logic; File Size62KB，6 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html; Environmental Compliance

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DS1005S-250+T&R Overview

Delay Lines / Timing Elements

DS1005S-250+T&R Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Maxim
Parts packaging code	SOIC
package instruction	SOP, SOP16,.4
Contacts	16
Reach Compliance Code	compliant
Other features	BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT
series	CMOS/TTL
Input frequency maximum value (fmax)	2.5 MHz
JESD-30 code	R-PDSO-G16
JESD-609 code	e3
length	10.335 mm
Logic integrated circuit type	SILICON DELAY LINE
Humidity sensitivity level	1
Number of functions	1
Number of taps/steps	5
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Maximum supply current (ICC)	70 mA
programmable delay line	NO
Prop。Delay @ Nom-Sup	250 ns
Certification status	Not Qualified
Maximum seat height	2.68 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	250 ns
width	7.51 mm
Base Number Matches	1

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DS1005

5-Tap Silicon Delay Line

www.dalsemi.com

FEATURES

All-silicon time delay

5 taps equally spaced

Delay tolerance ±2 ns or ±3%, whichever is

greater

Stable and precise over temperature and

voltage range

Leading and trailing edge accuracy

Economical

Auto-insertable, low profile

Standard 14-pin DIP, 8-pin DIP, or 16-pin

SOIC

Tape and reel available for surface-mount

Low-power CMOS

TTL/CMOS compatible

Vapor phase, IR and wave solderability

Custom delays available

Quick turn prototypes

Extended temperature range available

TAP 2

TAP 4

GND

PIN ASSIGNMENT

TAP 1

TAP 3

TAP 5

TAP 2

TAP 4

GND

TAP 1

TAP 3

TAP 5

DS1005 14-Pin DIP (300-mil)

See Mech. Drawings Section

DS1005S 16-Pin SOIC

(300-mil)

See Mech. Drawings Section

TAP 1

TAP 3

TAP 5

TAP 2

TAP 4

GND

DS1005M 8-Pin DIP (300-mil)

See Mech. Drawings Section

PIN DESCRIPTION

TAP 1-TAP 5

GND

- TAP Output Number

- +5 Volts

- Ground

- No Connection

- Input

DESCRIPTION

The DS1005 5-Tap Silicon Delay Line provides five equally spaced taps with delays ranging from 12 ns

to 250 ns, with an accuracy of

±2

ns or

±3%,

whichever is greater. This device is offered in a standard 14-

pin DIP, making it compatible with existing delay line products. Space-saving 8-pin DIPs and 16-pin

SOICs are also available. Both enhanced performance and superior reliability over hybrid technology is

achieved by the combination of a 100% silicon delay line and industry standard DIP and SOIC

packaging. In order to maintain complete pin compatibility, DIP packages are available with hybrid lead

configurations. The DS1005 reproduces the input logic level at each tap after the fixed delay specified by

the dash number in Table 1. The device is designed with both leading and trailing edge accuracy. Each

tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to

meet special needs. For special requests and rapid delivery, call (972) 371–4348.

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