Changes to Digital Outputs Section .............................................21
Changes to Timing Section............................................................22
Added Data Clock Output (DCO) Section..................................22
Changes to Configuration Using the SPI Section and
Configuration Without the SPI Section .......................................23
Changes to Table 15 ........................................................................25
Changes to Table 16 ........................................................................39
Changes to Ordering Guide...........................................................42
4/06—Revision 0: Initial Version
Rev. A | Page 3 of 44
AD9233
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS enabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
1
Integral Nonlinearity (INL)
1
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance
2
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD
1
IDRVDD
1
(DRVDD = 1.8 V)
IDRVDD
1
(DRVDD = 3.3 V)
POWER CONSUMPTION
DC Input
Sine Wave Input
1
(DRVDD = 1.8 V)
Sine Wave Input
1
(DRVDD = 3.3 V)
Standby
3
Power-Down
1
2
Temp
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
Full
25°C
Full
Full
Full
AD9233BCPZ-80
Min
Typ
Max
12
Guaranteed
±0.3
±0.5
±0.2
±4.7
±0.3
±0.2
±1.2
±0.5
±15
±95
±5
7
0.34
2
8
6
±20
AD9233BCPZ-105
Min
Typ
Max
12
Guaranteed
±0.3
±0.8
±0.2
±4.9
±0.5
±0.2
±1.2
±0.5
±15
±95
±5
7
0.34
2
8
6
±35
AD9233BCPZ-125
Min
Typ
Max
12
Guaranteed
±0.3
±0.8
±0.2
±3.9
±0.5
±0.2
±1.2
±0.5
±15
±95
±5
7
0.34
2
8
6
±35
Unit
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
mV
mV
LSB rms
V p-p
pF
kΩ
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
1.7
1.7
1.8
3.3
138
7
12
248
261
288
40
1.8
1.9
3.6
155
1.7
1.7
1.8
3.3
178
8
14
320
335
365
40
1.8
1.9
3.6
194
1.7
1.7
1.8
3.3
220
10
17
395
415
452
40
1.8
1.9
3.6
236
V
V
mA
mA
mA
mW
mW
mW
mW
mW
279
350
425
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.
3
Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).
Rev. A | Page 4 of 44
AD9233
AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS enabled, unless otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE-RATIO (SNR)
f
IN
= 2.4 MHz
f
IN
= 70 MHz
f
IN
= 100 MHz
f
IN
= 170 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
f
IN
= 2.4 MHz
f
IN
= 70 MHz
f
IN
= 100 MHz
f
IN
= 170 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
f
IN
= 2.4 MHz
f
IN
= 70 MHz
f
IN
= 100 MHz
f
IN
= 170 MHz
WORST SECOND OR THIRD HARMONIC
f
IN
= 2.4 MHz
f
IN
= 70 MHz
f
IN
= 100 MHz
f
IN
= 170 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
IN
= 2.4 MHz
f
IN
= 70 MHz
f
IN
= 100 MHz
f
IN
= 170 MHz
WORST OTHER (HARMONIC OR SPUR)
f
IN
= 2.4 MHz
f
IN
= 70 MHz
f
IN
= 100 MHz
f
IN
= 170 MHz
TWO-TONE SFDR
f
IN
= 30 MHz (−7 dBFS), 31 MHz (−7 dBFS)
f
IN
= 170 MHz (−7 dBFS), 171 MHz (−7 dBFS)
ANALOG INPUT BANDWIDTH
1
1
Temp
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
AD9233BCPZ-80
Min Typ
Max
69.5
69.5
68.9
69.4
68.9
69.2
69.2
68.5
69.1
68.6
11.4
11.4
11.4
11.3
−90.0
−85.0
−76.0
−85.0
−83.5
90.0
85.0
76.0
85.0
83.5
−90.0
−90.0
−85.0
−90.0
−90.0
87
83
650
AD9233BCPZ-105
Min Typ
Max
69.5
69.5
68.3
69.4
68.9
69.2
69.2
67.3
69.1
68.6
11.4
11.4
11.4
11.3
−90.0
−85.0
−73.0
−85.0
−83.5
90.0
85.0
73.0
85.0
83.5
−90.0
−90.0
−81.0
−90.0
−90.0
87
83
650
AD9233BCPZ-125
Min Typ
Max
69.5
69.5
68.3
69.4
68.9
69.2
69.2
67.3
69.1
68.6
11.4
11.4
11.4
11.3
−90.0
−85.0
−73.0
−85.0
−83.5
90.0
85.0
73.0
85.0
83.5
−90.0
−90.0
−81.0
−90.0
−90.0
85
84
650
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
MHz
See
AN-835,
Understanding High Speed ADC Testing and Evaluation,
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