19-6295; Rev 6/12
DS1218
Nonvolatile Controller
FEATURES
Converts CMOS RAM into nonvolatile
memories
Unconditionally write protects when V
CC
is
out of tolerance
Automatically switches to battery when
power fail occurs
Space saving 8-pin PDIP or 8-pin 150 mil SO
Packages
Consumes less than 100nA of battery current
PIN ASSIGNMENT
V
CCO
NC
NC
GND
1
2
3
4
8
7
6
5
V
CCI
V
BAT
CEO
CEI
PIN DESCRIPTION
V
CCI
V
CCO
NC
CEI
CEO
V
BAT
GND
- Input +5 Volt Supply
- RAM Power (V
CC
) Supply
- Chip Enable Input
- No Connection
- Chip Enable Output
- + Battery
- Ground
The DS1218 is a CMOS circuit which solves the application problems of converting CMOS RAM into
nonvolatile memory. Incoming power is monitored for an out-of-tolerance condition. When such a
condition is detected, the chip enable output is inhibited to accomplish write protection and the battery is
switched on to supply RAM with uninterrupted power. Special circuitry uses a low-leakage CMOS
process which affords precise voltage detection at extremely low battery consumption. The 8-pin package
keeps PC board real estate requirements to a minimum. By combining the DS1218 nonvolatile controller
chip with a full CMOS memory and lithium batteries, 10 years of nonvolatile RAM operation can be
achieved.
The DS1218 Nonvolatile Controller performs the circuit functions required to battery back-up a RAM.
First, a switch is provided to direct power from the battery or V
CCI
supply, depending on which is greater.
This switch has a voltage drop of less than 0.2V. The second function which the nonvolatile controller
provides is power-fail detection. The DS1218 constantly monitors the V
CC
supply. When V
CCI
falls to
1.26 times the battery voltage, a precision comparator outputs a power-fail detect signal to the chip enable
logic. The third function of write protection is accomplished by holding the chip enable output signal to
within 0.2V of the V
CCI
or battery supply, when a power-fail condition is detected.
During nominal supply conditions, the chip enable output will follow chip enable input with a maximum
propagation delay of 10 ns.
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DESCRIPTION
OPERATION
Voltage Range on Any Pin Relative to Ground
Operating Temperature Range
Storage Temperature Range
Soldering Temperature (reflow, SO)
Lead Temperature (soldering, 10s)
ABSOLUTE MAXIMUM RATINGS
DS1218
-0.5V to +7.0V
0°C to +70°C
-55°C to +125°C
+260°C
+300°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
PDIP
SO
Junction-to-Ambient Thermal Resistance (θ
JA
).…………………...……………………....110°C/W
Junction-to-Case Thermal Resistance (θ
JC
)…………………………………………………40°C/W
Junction-to-Ambient Thermal Resistance (θ
JA
).…………………………………………...136°C/W
Junction-to-Case Thermal Resistance (θ
JC
)…………………………………………………38°C/W
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board for the SO. For detailed information on package thermal considerations, refer to
www.maxim-ic.com/thermal-tutorial.
Note 1:
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply
Logic 1
Logic 0
Battery Supply
SYMBOL
V
CCI
V
IH
V
IL
V
BAT
SYMBOL
I
CCI
I
BAT
I
CCO
I
CCO
I
IL
I
OH
I
OL
V
CCTP
SYMBOL
C
IN
C
OUT
-1.0
-1.0
MIN
4.5
2.0
-0.3
2.5
MIN
TYP
5.0
3.0
TYP
2
MAX
5.5
5.5
0.8
3.5
MAX
5
100
80
UNITS
V
V
V
V
UNITS
mA
nA
mA
mA
(0°C to +70°C)
NOTES
2
2
2
2
NOTES
4
4, 5
6
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Active Current
Battery Current
RAM Current
(V
CCO1
≥
V
CCI
-0.3V)
RAM Current
(V
CCO
≥
V
CCI
-0.2V)
Input Leakage
CEO
Output @ 2.4V
CEO
Output @ 0.4V
V
CC
Trip Point
PARAMETER
Input Capacitance
Output Capacitance
(0°C to +70°C; V
CCI
= 5V ± 10%)
70
+1.0
4.0
1.26xV
BAT
MIN
TYP
MAX
5
7
µA
mA
mA
CAPACITANCE
UNITS
pF
pF
(T
A
= +25°C)
NOTES
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DS1218
AC ELECTRICAL CHARACTERISTICS
PARAMETER
CE
Propagation Delay
Recovery at Power-up
V
CC
Slew Rate
CE
Pulse Width
SYMBOL
t
PD
t
REC
t
F
t
CE
MIN
0.2
500
(0°C to +70°C; V
CC
= 5.0V ± 10%)
TYP
4
MAX
10
2
1.5
UNITS
ns
ms
µs
µs
NOTES
3
7, 8
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TIMING DIAGRAM: POWER-UP
DS1218
TIMING DIAGRAM: POWER-DOWN
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NOTES:
DS1218
2. All voltages referenced to ground.
3. Measured with a load as shown in Figure 1.
4. Outputs open.
5. Drain from battery when V
CC
< V
BAT
.
6. Maximum amount of current which can be drawn through pin 1 of the controller.
7. t
CE
max must be met to ensure data integrity on power loss.
8.
CEO
can only sustain leakage current in the battery backup mode.
OUTPUT LOAD
Figure 1
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