Low Skew, 1-to-12 Differential-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
Datasheet
83948I
General Description
The 83948I is a low skew, 1-to-12 Differential-to-LVCMOS/LVTTL
Fanout Buffer and a member of the family of High Performance
Clock Solutions from IDT. The 83948I has two selectable clock
inputs. The CLK, nCLK pair can accept most standard differential
input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL
input levels. The low impedance LVCMOS/LVTTL outputs are
designed to drive 50 series or parallel terminated transmission
lines. The effective fanout can be increased from 12 to 24 by
utilizing the ability of the outputs to drive two series terminated
lines.
The 83948I is characterized at full 3.3V core/3.3V output.
Guaranteed output and part-to-part skew characteristics make the
83948I ideal for those clock distribution applications demanding
well defined performance and repeatability.
Features
•
•
•
•
•
•
•
•
•
•
•
Twelve LVCMOS/LVTTL outputs
Selectable differential CLK/nCLK or LVCMOS/LVTTL clock
input
CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
Maximum output frequency: 250MHz
Output skew: 350ps (maximum)
Part-to-part skew: 1.5ns (maximum)
3.3V core, 3.3V output
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
For drop in replacement part use 83948i-147
Pin Assignment
GND
Q0
Q
LVCMOS_CLK
Pullup
CLK
nCLK
Pulldown
CLK_SEL
Pullup
Pullup
32 31 30 29 28 27 26 25
1
0
Q0
Q1
Q2
Q3
CLK_SEL
LVCMOS_CLK
CLK
nCLK
CLK_EN
1
2
3
4
5
6
7
8
9
Q11
Q3
Q1
Q2
D
V
DDO
V
DDO
CLK_EN
Pullup
GND
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
V
DDO
GND
V
DDO
GND
Q10
Q9
Q8
GND
Q4
V
DDO
Q5
GND
Q6
V
DDO
Q7
Block Diagram
OE
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
V
DD
GND
83948I
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
OE
Pullup
©2016 Integrated Device Technology, Inc
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83948I Datasheet
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8, 12, 16,
20, 24, 28, 32
9, 11, 13,
15, 17, 19,
21, 23, 25,
27, 29, 31
10, 14, 18,
22, 26, 30
Name
CLK_SEL
LVCMOS_CLK
CLK
nCLK
CLK_EN
OE
V
DD
GND
Q11, Q10, Q9,
Q8, Q7, Q6,
Q5, Q4, Q3,
Q2, Q1, Q0
V
DDO
Input
Input
Input
Input
Input
Input
Power
Power
Type
Pullup
Pullup
Pullup
Pulldown
Pullup
Pullup
Description
Clock select input. When HIGH, selects LVCMOS_CLK input.
When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Clock enable pin. LVCMOS/LVTTL interface levels.
Output enable pin. LVCMOS/LVTTL interface levels.
Positive supply pin.
Power supply ground.
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power
Output supply pins.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
25
7
Maximum
Units
pF
k
k
pF
R
PULLDOWN
Input Pulldown Resistor
C
PD
R
OUT
Power Dissipation Capacitance
(per output)
Output Impedance
Function Tables
Table 3A. Clock Select Function Table
Control Input
CLK_SEL
0
1
CLK/nCLK
Selected
De-selected
Clock
LVCMOS_CLK
De-selected
Selected
©2016 Integrated Device Technology, Inc
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83948I Datasheet
Table 3B. Clock Input Function Table
Inputs
CLK_SEL
0
0
0
0
0
0
1
1
LVCMOS_CLK
–
–
–
–
–
–
0
1
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
–
–
nCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
–
–
Outputs
Q[0:11]
LOW
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Single-Ended
Differential to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
Non-Inverting
Non-Inverting
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
47.9C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.0
3.0
Typical
3.3
3.3
Maximum
3.6
3.6
55
Units
V
V
mA
©2016 Integrated Device Technology, Inc
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83948I Datasheet
Table 4B. DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
V
PP
V
CMR
I
IN
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
Input Current
Output High Voltage
Output Low Voltage
I
OH
= -20mA
I
OL
= 20mA
2.5
0.4
Test Conditions
Minimum
2
-0.3
0.15
GND + 0.5
Typical
Maximum
V
DD
+ 0.3
0.8
1.3
V
DD
– 0.85
±100
Units
V
V
V
V
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= V
DDO
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Parameter
f
MAX
Symbol
Output Frequency
CLK/nCLK;
NOTE 1A
LVCMOS_CLK;
NOTE 1B
ƒ
150MHz
ƒ
150MHz
Measured on
Rising Edge @ V
DDO
/2
Measured on
Rising Edge @ V
DDO
/2
0.8V to 2V
ƒ < 150MHz
0.2
t
Cycle
/2 - 800
2.25
2
Test Conditions
Minimum
Typical
Maximum
250
3.75
4
350
1.5
2
1.0
t
Cycle
/2 + 800
11
11
1
0
1
1
Units
MHz
ns
ns
ps
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
t
PD
Propagation Delay
tsk(o)
tsk(pp)
t
R
/ t
F
t
PW
t
PZL,
t
PZH
t
PLZ,
t
PHZ
Output Skew; NOTE 2, 6
Part-to-Part Skew;
NOTE 3, 6
CLK/nCLK
LVCMOS_CLK
Output Rise/Fall Time
Output Pulse Width
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
Clock Enable
Setup Time;
NOTE 5
Clock Enable
Hold Time;
NOTE 5
CLK_EN to
CLK/nCLK
CLK_EN to
LVCMOS_CLK
CLK/nCLK to
CLK_EN
LVCMOS_CLK to
CLK_EN
t
S
t
H
NOTE 1A: Measured from the differential input crossing point to V
DDO
/2 of the output.
NOTE 1B: Measured from V
DD
/2 or crosspoint of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
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83948I Datasheet
Parameter Measurement Information
1.65V±0.15V
VDD
V
DD,
V
DDO
SCOPE
Qx
nCLK
V
PP
Cross Points
V
CMR
CLK
GND
GND
-1.65V±0.15V
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
Differential Input Level
Part 1
V
Qx
DDO
V
Qx
DDO
2
Part 2
V
DDO
2
V
Qy
DDO
Qy
2
tsk(pp)
2
tsk(o)
Part-to-Part Skew
Output Skew
2V
0.8V
Q0:Q11
2V
Q0:Q11
V
DDO
2
t
PW
V
DDO
2
V
DDO
2
0.8V
t
R
t
F
odc =
t
PERIOD
t
PW
t
PERIOD
Output Rise/Fall Time
Output Pulse Width
©2016 Integrated Device Technology, Inc
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May 19, 2016
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