Preliminary
GS8162Z72CC-xxxV
209-Bump BGA
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• On-chip parity encoding and error detection
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 209-Bump BGA package
• RoHS-compliant 209-Bump BGA package available
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–150 MHz
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8162Z72CC-xxxV may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8162Z72CC-xxxV is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 209-bump BGA package.
Functional Description
The GS8162Z72CC-xxxV is an 18Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Parameter Synopsis
-250
Pipeline
3-1-1-1
Flow Through
2-1-1-1
t
KQ
tCycle
Curr
t
KQ
tCycle
Curr
3.0
4.0
425
5.5
5.5
315
-200
3.0
5.0
345
6.5
6.5
275
-150
3.8
6.7
270
7.5
7.5
250
Unit
ns
ns
mA
ns
ns
mA
Rev: 1.02a 6/2006
1/27
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z72CC-xxxV
GS8162Z72CC-xxxV Pad Out—209-Bump BGA—Top View (Package C)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Rev 10
DQG
DQG
DQG
DQG
DQPG
DQC
DQC
DQC
DQC
NC
DQH
DQH
DQH
DQH
DQPD
DQD
DQD
DQD
DQD
2
DQG
DQG
DQG
DQG
DQPC
DQC
DQC
DQC
DQC
NC
DQH
DQH
DQH
DQH
DQPH
DQD
DQD
DQD
DQD
3
A
BC
BH
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TMS
4
E2
BG
BD
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDI
5
A
NC
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
A
A
6
ADV
W
E1
G
V
DD
ZQ
MCH
MCL
MCH
CKE
FT
MCL
MCH
ZZ
V
DD
LBO
A
A1
A0
7
A
A
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
A
A
8
E3
BB
BE
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDO
9
A
BF
BA
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TCK
10
DQB
DQB
DQB
DQB
DQPF
DQF
DQF
DQF
DQF
NC
DQA
DQA
DQA
DQA
DQPA
DQE
DQE
DQE
DQE
11
DQB
DQB
DQB
DQB
DQPB
DQF
DQF
DQF
DQF
NC
DQA
DQA
DQA
DQA
DQPE
DQE
DQE
DQE
DQE
11 x 19 Bump BGA—14 x 22 mm
2
Body—1 mm Bump Pitch
Rev: 1.02a 6/2006
2/27
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z72CC-xxxV
GS8162Z72CC-xxxV BGA Pin Description
Symbol
A
0
, A
1
A
DQ
A
DQ
B
DQ
C
DQ
D
DQ
E
DQ
F
DQ
G
DQ
H
B
A
, B
B
, B
C
,B
D,
B
E
, B
F
,
B
G
,B
H
NC
CK
W
E
1,
E
3
E
2
G
ADV
ZZ
FT
LBO
MCH
MCL
CKE
BW
ZQ
TMS
TDI
TDO
TCK
V
DD
V
SS
V
DDQ
I
I
I
I
I
O
I
I
I
I
Type
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
I/O
Data Input and Output pins
I
—
I
I
I
I
I
I
I
I
I
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D,
DQ
E
,
DQ
F
, DQ
G
, DQ
H
I/Os; active low
No Connect
Clock Input Signal; active high
Write Enable. Writes all enabled bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active high
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Must Connect High
Must Connect Low
Clock Enable; active low
Byte Enable; active low
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.02a 6/2006
3/27
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z72CC-xxxV
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E
1
, E
2,
and E
3
). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
W
H
L
L
L
L
L
L
B
A
X
L
H
H
H
L
H
B
B
X
H
L
H
H
L
H
B
C
X
H
H
L
H
L
H
B
D
X
H
H
H
L
L
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E
1
, E
2,
and E
3
) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is asserted low, and the Write input is sampled low at the rising edge of
clock. The Byte Write Enable inputs (B
A
, B
B
, B
C,
and B
D
) determine which bytes will be written. All or none may be activated. A
write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.02a 6/2006
4/27
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z72CC-xxxV
Synchronous Truth Table
Operation
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
Write Abort, Continue Burst
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle
Deselect Cycle, Continue
Sleep Mode
Clock Edge Ignore, Stall
Type Address CK CKE ADV W Bx E
1
E
2
E
3
G ZZ
R
B
R
B
W
B
B
D
D
D
D
D
External
Next
External
Next
External
Next
Next
None
None
None
None
None
None
Current
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
L-H
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
H
L
H
L
H
H
L
L
L
L
H
X
X
H
X
H
X
L
X
X
X
X
X
L
X
X
X
X
X
X
X
L
L
H
X
X
X
H
X
X
X
L
X
L
X
L
X
X
H
X
X
L
X
X
X
H
X
H
X
H
X
X
X
X
L
H
X
X
X
L
X
L
X
L
X
X
X
H
X
L
X
X
X
L
L
H
H
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
H
L
DQ
Q
Q
High-Z
High-Z
D
D
Notes
1,10
2
1,2,10
3
1,3,10
High-Z 1,2,3,10
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
-
4
1
1
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.02a 6/2006
5/27
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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