GS8162Z72CC-V datasheet, PDF - EEWORLD Datasheet

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GS8162Z72CC-V: Description18Mb Pipelined and Flow Through Synchronous NBT SRAM; File Size760KB，27 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8162Z72CC-V Overview

18Mb Pipelined and Flow Through Synchronous NBT SRAM

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Preliminary

GS8162Z72CC-xxxV

209-Bump BGA

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip write parity checking; even or odd selectable

• On-chip parity encoding and error detection

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 8M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 209-Bump BGA package

• RoHS-compliant 209-Bump BGA package available

18Mb Pipelined and Flow Through

Synchronous NBT SRAM

250 MHz–150 MHz

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8162Z72CC-xxxV may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising edge triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge-triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS8162Z72CC-xxxV is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 209-bump BGA package.

Functional Description

The GS8162Z72CC-xxxV is an 18Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Parameter Synopsis

-250

Pipeline

3-1-1-1

Flow Through

2-1-1-1

tCycle

Curr

tCycle

Curr

3.0

4.0

425

5.5

315

-200

3.0

5.0

345

6.5

275

-150

3.8

6.7

270

7.5

250

Unit

Rev: 1.02a 6/2006

1/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z72CC-V Related Products

	GS8162Z72CC-V	GS8162Z72CGC-250IV	GS8162Z72CGC-150IV
Description	18Mb Pipelined and Flow Through Synchronous NBT SRAM	18Mb Pipelined and Flow Through Synchronous NBT SRAM	18Mb Pipelined and Flow Through Synchronous NBT SRAM
Is it lead-free?	-	Lead free	Lead free
Is it Rohs certified?	-	conform to	conform to
Maker	-	GSI Technology	GSI Technology
Parts packaging code	-	BGA	BGA
package instruction	-	LBGA,	LBGA,
Contacts	-	209	209
Reach Compliance Code	-	compli	compli
ECCN code	-	3A991.B.2.B	3A991.B.2.B
Factory Lead Time	-	8 weeks	8 weeks
Maximum access time	-	5.5 ns	7.5 ns
Other features	-	FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES WITH 2.5V SUPPLY	FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES WITH 2.5V SUPPLY
JESD-30 code	-	R-PBGA-B209	R-PBGA-B209
JESD-609 code	-	e1	e1
length	-	22 mm	22 mm
memory density	-	18874368 bi	18874368 bi
Memory IC Type	-	ZBT SRAM	ZBT SRAM
memory width	-	72	72
Humidity sensitivity level	-	3	3
Number of functions	-	1	1
Number of terminals	-	209	209
word count	-	262144 words	262144 words
character code	-	256000	256000
Operating mode	-	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	-	85 °C	85 °C
Minimum operating temperature	-	-40 °C	-40 °C
organize	-	256KX72	256KX72
Package body material	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	LBGA	LBGA
Package shape	-	RECTANGULAR	RECTANGULAR
Package form	-	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Parallel/Serial	-	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	-	260	260
Certification status	-	Not Qualified	Not Qualified
Maximum seat height	-	1.7 mm	1.7 mm
Maximum supply voltage (Vsup)	-	2 V	2 V
Minimum supply voltage (Vsup)	-	1.7 V	1.7 V
Nominal supply voltage (Vsup)	-	1.8 V	1.8 V
surface mount	-	YES	YES
technology	-	CMOS	CMOS
Temperature level	-	INDUSTRIAL	INDUSTRIAL
Terminal surface	-	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	-	BALL	BALL
Terminal pitch	-	1 mm	1 mm
Terminal location	-	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	-	NOT SPECIFIED	NOT SPECIFIED
width	-	14 mm	14 mm

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